[PATCH] D16625: [mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions

[Simon Dardis via llvm-commits]

sdardis requested changes to this revision.
sdardis added a comment.
This revision now requires changes to proceed.

One last change, can you get these instructions into the instruction mapping tables? That way some existing optimisations will fire properly, e.g. the patterns around Mips64InstrInfo.cpp:561.


================
Comment at: lib/Target/Mips/MicroMips64r6InstrInfo.td:278-280
@@ +277,5 @@
+
+class DSRL_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsrl", uimm5,
+                                                 GPR64Opnd, II_DSRL,
+                                                 srl, immZExt5>;
+class DSRL32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsrl32", uimm5,
----------------
Similar to the DROTR change I requested, can you change this so that it takes a uimm6 & modify MipsMCCodeEmitter to pick dsrl/dsrl32 depending on the immediate. See also Daniel's comment in  D16917.

================
Comment at: lib/Target/Mips/Mips64InstrInfo.td:139-152
@@ -138,18 +138,16 @@
 /// Shift Instructions
 let AdditionalPredicates = [NotInMicroMips] in {
   def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
                SRA_FM<0x38, 0>, ISA_MIPS3;
+  def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
+               SRA_FM<0x3a, 0>, ISA_MIPS3;
 }
-def DSRL   : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
-             SRA_FM<0x3a, 0>, ISA_MIPS3;
 let AdditionalPredicates = [NotInMicroMips] in {
   def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
              SRA_FM<0x3b, 0>, ISA_MIPS3;
 }
 let AdditionalPredicates = [NotInMicroMips] in {
   def DSLLV  : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
              SRLV_FM<0x14, 0>, ISA_MIPS3;
 }
 let AdditionalPredicates = [NotInMicroMips] in {
----------------
These blocks can be joined.

================
Comment at: lib/Target/Mips/Mips64InstrInfo.td:153-168
@@ -152,18 +152,18 @@
 }
-def DSRLV  : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
-             SRLV_FM<0x16, 0>, ISA_MIPS3;
 let AdditionalPredicates = [NotInMicroMips] in {
   def DSRAV  : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
                SRLV_FM<0x17, 0>, ISA_MIPS3;
+  def DSRLV  : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
+               SRLV_FM<0x16, 0>, ISA_MIPS3;
 }
 let AdditionalPredicates = [NotInMicroMips] in {
   def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
                SRA_FM<0x3c, 0>, ISA_MIPS3;
+  def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
+               SRA_FM<0x3e, 0>, ISA_MIPS3;
 }
-def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
-             SRA_FM<0x3e, 0>, ISA_MIPS3;
 let AdditionalPredicates = [NotInMicroMips] in {
   def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
                SRA_FM<0x3f, 0>, ISA_MIPS3;
 }
 
----------------
And these too.

================
Comment at: lib/Target/Mips/Mips64InstrInfo.td:608
@@ -597,2 +607,3 @@
 
+
 // Atomic store patterns.
----------------
Drop this newline

================
Comment at: lib/Target/Mips/Mips64r6InstrInfo.td:118
@@ -117,2 +117,3 @@
   def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
+  def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6;
 }
----------------
This also needs to be added to the instruction mapping table.


http://reviews.llvm.org/D16625