[PATCH] D21067: [AVX512] Fix load opcode for fast isel.

[Igor Breger via llvm-commits]

igorb updated this revision to Diff 59873.
igorb added a comment.

Test case added.


Repository:
  rL LLVM

http://reviews.llvm.org/D21067

Files:
  lib/Target/X86/X86FastISel.cpp
  test/CodeGen/X86/fast-isel-vecload.ll

Index: test/CodeGen/X86/fast-isel-vecload.ll
===================================================================
--- test/CodeGen/X86/fast-isel-vecload.ll
+++ test/CodeGen/X86/fast-isel-vecload.ll
@@ -1,5 +1,6 @@
 ; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE --check-prefix=ALL
 ; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=AVX --check-prefix=ALL
+; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-unknown -mattr=+avx512f < %s | FileCheck %s --check-prefix=KNL --check-prefix=ALL
 
 ; Verify that fast-isel knows how to select aligned/unaligned vector loads.
 ; Also verify that the selected load instruction is in the correct domain.
@@ -183,3 +184,23 @@
   %0 = load <2 x double>, <2 x double>* %V
   ret <2 x double> %0
 }
+
+define <8 x i64> @test_v8i64_alignment(<8 x i64>* %V) {
+; KNL-LABEL: test_v8i64_alignment:
+; KNL:       # BB#0: # %entry
+; KNL-NEXT:    vmovdqa64 (%rdi), %zmm0
+; KNL-NEXT:    retq
+entry:
+  %0 = load <8 x i64>, <8 x i64>* %V, align 64
+  ret <8 x i64> %0
+}
+
+define <8 x i64> @test_v8i64(<8 x i64>* %V) {
+; KNL-LABEL: test_v8i64:
+; KNL:       # BB#0: # %entry
+; KNL-NEXT:    vmovdqu64 (%rdi), %zmm0
+; KNL-NEXT:    retq
+entry:
+  %0 = load <8 x i64>, <8 x i64>* %V, align 4
+  ret <8 x i64> %0
+}
Index: lib/Target/X86/X86FastISel.cpp
===================================================================
--- lib/Target/X86/X86FastISel.cpp
+++ lib/Target/X86/X86FastISel.cpp
@@ -452,7 +452,7 @@
     assert(Subtarget->hasAVX512());
     // Note: There are a lot more choices based on type with AVX-512, but
     // there's really no advantage when the load isn't masked.
-    Opc = (Alignment >= 64) ? X86::VMOVDQA64Zmr : X86::VMOVDQU64Zmr;
+    Opc = (Alignment >= 64) ? X86::VMOVDQA64Zrm : X86::VMOVDQU64Zrm;
     RC  = &X86::VR512RegClass;
     break;
   }


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