[PATCH] D21009: Legalize FMINNAN and FMAXNAN during float16 promotion

[Pirama Arumuga Nainar via llvm-commits]

pirama created this revision.
pirama added a reviewer: jmolloy.
pirama added subscribers: srhines, llvm-commits.

Folding of setcc + select to fminnan or fmaxnan can happen for float16
since this folding is conditioned on the eventual legalized type (float,
in this case).  Promote result of FMINNAN and FMAXNAN nodes just like
other binary nodes.

http://reviews.llvm.org/D21009

Files:
  lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
  test/CodeGen/ARM/fp16-promote.ll
  test/CodeGen/ARM/vminmaxnm.ll

Index: test/CodeGen/ARM/vminmaxnm.ll
===================================================================
--- test/CodeGen/ARM/vminmaxnm.ll
+++ test/CodeGen/ARM/vminmaxnm.ll
@@ -372,6 +372,19 @@
   ret float %cond2
 }
 
+define half @fp-armv8_vminmaxnm_f16_promote(half %p) #0 {
+; CHECK-LABEL: "fp-armv8_vminmaxnm_f16_promote":
+; CHECK-NOT: vcmp
+; CHECK: vminnm.f32
+; CHECK: vmaxnm.f32
+  %cmp1 = fcmp fast ugt half 0xHBC00, %p
+  %cond1 = select i1 %cmp1, half %p, half 0xHBC00
+  %cmp2 = fcmp fast ult half 0xHBC99, %cond1
+  %cond2 = select i1 %cmp2, half %cond1, half 0xHBC99
+  ret half %cond2
+}
+
+
 declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
 declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
 declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
Index: test/CodeGen/ARM/fp16-promote.ll
===================================================================
--- test/CodeGen/ARM/fp16-promote.ll
+++ test/CodeGen/ARM/fp16-promote.ll
@@ -929,4 +929,15 @@
   ret half %r
 }
 
+; CHECK-LABEL: test_f16_fminmaxnan:
+; CHECK: vmin.f32
+; CHECK: vmax.f32
+define half @test_f16_fminmaxnan(half %p) #0 {
+  %cmp1 = fcmp ugt half 0xHBC00, %p
+  %cond1 = select i1 %cmp1, half %p, half 0xHBC00
+  %cmp2 = fcmp ult half 0xHBC99, %cond1
+  %cond2 = select i1 %cmp2, half %cond1, half 0xHBC99
+  ret half %cond2
+}
+
 attributes #0 = { nounwind }
Index: lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -1869,7 +1869,9 @@
     case ISD::FADD:
     case ISD::FDIV:
     case ISD::FMAXNUM:
+    case ISD::FMAXNAN:
     case ISD::FMINNUM:
+    case ISD::FMINNAN:
     case ISD::FMUL:
     case ISD::FPOW:
     case ISD::FREM:


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