[PATCH] D20916: [WIP][mips] Allow explicit ABI's in MIPS triples within LLVM.

[Daniel Sanders via llvm-commits]

dsanders updated this revision to Diff 59505.
dsanders added a comment.

top the backend determining the ABI from the CPU. The API user should work this out.
Make the calls to getABIVariant() unconditional.


http://reviews.llvm.org/D20916

Files:
  include/llvm/ADT/Triple.h
  include/llvm/MC/MCTargetOptionsCommandFlags.h
  lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  lib/CodeGen/TargetLoweringBase.cpp
  lib/Support/Triple.cpp
  lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
  test/CodeGen/ARM/arm-abi-attr.ll
  test/CodeGen/ARM/atomic-64bit.ll
  test/CodeGen/ARM/dagcombine-concatvector.ll
  test/CodeGen/ARM/emit-big-cst.ll
  test/CodeGen/ARM/tail-call.ll
  test/CodeGen/Mips/2008-08-01-AsmInline.ll
  test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll
  test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll
  test/CodeGen/Mips/abiflags32.ll
  test/CodeGen/Mips/adjust-callstack-sp.ll
  test/CodeGen/Mips/atomicCmpSwapPW.ll
  test/CodeGen/Mips/blockaddr.ll
  test/CodeGen/Mips/cconv/arguments-float.ll
  test/CodeGen/Mips/cconv/arguments-fp128.ll
  test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
  test/CodeGen/Mips/cconv/arguments-hard-float.ll
  test/CodeGen/Mips/cconv/arguments-hard-fp128.ll
  test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll
  test/CodeGen/Mips/cconv/arguments-struct.ll
  test/CodeGen/Mips/cconv/arguments-varargs.ll
  test/CodeGen/Mips/cconv/arguments.ll
  test/CodeGen/Mips/cconv/callee-saved-float.ll
  test/CodeGen/Mips/cconv/callee-saved.ll
  test/CodeGen/Mips/cconv/memory-layout.ll
  test/CodeGen/Mips/cconv/reserved-space.ll
  test/CodeGen/Mips/cconv/return-float.ll
  test/CodeGen/Mips/cconv/return-hard-float.ll
  test/CodeGen/Mips/cconv/return-hard-fp128.ll
  test/CodeGen/Mips/cconv/return-hard-struct-f128.ll
  test/CodeGen/Mips/cconv/return-struct.ll
  test/CodeGen/Mips/cconv/return.ll
  test/CodeGen/Mips/cconv/roundl-call.ll
  test/CodeGen/Mips/cconv/stack-alignment.ll
  test/CodeGen/Mips/compactbranches/compact-branches.ll
  test/CodeGen/Mips/dynamic-stack-realignment.ll
  test/CodeGen/Mips/ehframe-indirect.ll
  test/CodeGen/Mips/elf_eflags.ll
  test/CodeGen/Mips/fcopysign-f32-f64.ll
  test/CodeGen/Mips/fcopysign.ll
  test/CodeGen/Mips/fmadd1.ll
  test/CodeGen/Mips/fp-indexed-ls.ll
  test/CodeGen/Mips/fp16-promote.ll
  test/CodeGen/Mips/fpxx.ll
  test/CodeGen/Mips/global-address.ll
  test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll
  test/CodeGen/Mips/inlineasm64.ll
  test/CodeGen/Mips/interrupt-attr-64-error.ll
  test/CodeGen/Mips/largeimmprinting.ll
  test/CodeGen/Mips/llvm-ir/add.ll
  test/CodeGen/Mips/llvm-ir/lh_lhu.ll
  test/CodeGen/Mips/llvm-ir/mul.ll
  test/CodeGen/Mips/llvm-ir/sdiv.ll
  test/CodeGen/Mips/llvm-ir/srem.ll
  test/CodeGen/Mips/llvm-ir/udiv.ll
  test/CodeGen/Mips/llvm-ir/urem.ll
  test/CodeGen/Mips/load-store-left-right.ll
  test/CodeGen/Mips/longbranch.ll
  test/CodeGen/Mips/madd-msub.ll
  test/CodeGen/Mips/mips64-sret.ll
  test/CodeGen/Mips/mips64directive.ll
  test/CodeGen/Mips/mips64ext.ll
  test/CodeGen/Mips/mips64extins.ll
  test/CodeGen/Mips/mips64fpimm0.ll
  test/CodeGen/Mips/mips64fpldst.ll
  test/CodeGen/Mips/mips64intldst.ll
  test/CodeGen/Mips/mips64r6/compatibility.ll
  test/CodeGen/Mips/msa/basic_operations.ll
  test/CodeGen/Mips/msa/basic_operations_float.ll
  test/CodeGen/Mips/named-register-n32.ll
  test/CodeGen/Mips/remat-immed-load.ll
  test/CodeGen/Mips/start-asm-file.ll
  test/CodeGen/Mips/zeroreg.ll
  test/CodeGen/PowerPC/ppc64-elf-abi.ll
  test/MC/Mips/cpload.s
  test/MC/Mips/cprestore-noreorder-noat.s
  test/MC/Mips/cprestore-noreorder.s
  test/MC/Mips/cprestore-reorder.s
  test/MC/Mips/cpsetup.s
  test/MC/Mips/do_switch3.s
  test/MC/Mips/elf_eflags.s
  test/MC/Mips/elf_reginfo.s
  test/MC/Mips/expansion-jal-sym-pic.s
  test/MC/Mips/macro-la-bad.s
  test/MC/Mips/macro-la.s
  test/MC/Mips/macro-li-bad.s
  test/MC/Mips/mips-expansions-bad.s
  test/MC/Mips/mips-reginfo-fp64.s
  test/MC/Mips/mips64-register-names-n32-n64.s
  test/MC/Mips/mips64-register-names-o32.s
  test/MC/Mips/mips64/abiflags.s
  test/MC/Mips/mips64extins.ll
  test/MC/Mips/mips64extins.s
  test/MC/Mips/mips64r2/abi-bad.s
  test/MC/Mips/mips64r2/abiflags.s
  test/MC/Mips/mips64r3/abi-bad.s
  test/MC/Mips/mips64r3/abiflags.s
  test/MC/Mips/mips64r5/abi-bad.s
  test/MC/Mips/mips64r5/abiflags.s
  test/MC/Mips/mips_abi_flags_xx.s
  test/MC/Mips/nabi-regs.s
  test/MC/Mips/nooddspreg-cmdarg.s
  test/MC/Mips/nooddspreg.s
  test/MC/Mips/oddspreg.s
  test/MC/Mips/reloc-directive-bad.s
  test/MC/Mips/reloc-directive-negative.s
  test/MC/Mips/reloc-directive.s
  tools/llc/llc.cpp
  tools/llvm-mc/llvm-mc.cpp
  unittests/ADT/TripleTest.cpp

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D20916.59505.patch
Type: text/x-patch
Size: 164518 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20160603/00016cc7/attachment-0001.bin>