[llvm] r271628 - [AVX512] Fix shuffle comment printing for EVEX encoded PSHUFD, PSHUFHW, and PSHUFLW.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 2 22:31:00 PDT 2016
Author: ctopper
Date: Fri Jun 3 00:31:00 2016
New Revision: 271628
URL: http://llvm.org/viewvc/llvm-project?rev=271628&view=rev
Log:
[AVX512] Fix shuffle comment printing for EVEX encoded PSHUFD, PSHUFHW, and PSHUFLW.
Modified:
llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp
llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll
llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll
llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll
Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp?rev=271628&r1=271627&r2=271628&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp (original)
+++ llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp Fri Jun 3 00:31:00 2016
@@ -62,13 +62,13 @@ using namespace llvm;
CASE_AVX_INS_COMMON(Inst, Y, r##src) \
CASE_SSE_INS_COMMON(Inst, r##src)
-#define CASE_SHUF(Inst, src) \
- CASE_AVX512_INS_COMMON(Inst, Z, r##src##i) \
- CASE_AVX512_INS_COMMON(Inst, Z256, r##src##i) \
- CASE_AVX512_INS_COMMON(Inst, Z128, r##src##i) \
- CASE_AVX_INS_COMMON(Inst, , r##src##i) \
- CASE_AVX_INS_COMMON(Inst, Y, r##src##i) \
- CASE_SSE_INS_COMMON(Inst, r##src##i)
+#define CASE_SHUF(Inst, suf) \
+ CASE_AVX512_INS_COMMON(Inst, Z, suf) \
+ CASE_AVX512_INS_COMMON(Inst, Z256, suf) \
+ CASE_AVX512_INS_COMMON(Inst, Z128, suf) \
+ CASE_AVX_INS_COMMON(Inst, , suf) \
+ CASE_AVX_INS_COMMON(Inst, Y, suf) \
+ CASE_SSE_INS_COMMON(Inst, suf)
#define CASE_VPERM(Inst, src) \
CASE_AVX512_INS_COMMON(Inst, Z, src##i) \
@@ -358,14 +358,10 @@ bool llvm::EmitAnyX86InstComments(const
ShuffleMask);
break;
- case X86::PSHUFDri:
- case X86::VPSHUFDri:
- case X86::VPSHUFDYri:
+ CASE_SHUF(PSHUFD, ri)
Src1Name = getRegName(MI->getOperand(1).getReg());
// FALL THROUGH.
- case X86::PSHUFDmi:
- case X86::VPSHUFDmi:
- case X86::VPSHUFDYmi:
+ CASE_SHUF(PSHUFD, mi)
DestName = getRegName(MI->getOperand(0).getReg());
if (MI->getOperand(NumOperands - 1).isImm())
DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::i32, 0),
@@ -373,14 +369,10 @@ bool llvm::EmitAnyX86InstComments(const
ShuffleMask);
break;
- case X86::PSHUFHWri:
- case X86::VPSHUFHWri:
- case X86::VPSHUFHWYri:
+ CASE_SHUF(PSHUFHW, ri)
Src1Name = getRegName(MI->getOperand(1).getReg());
// FALL THROUGH.
- case X86::PSHUFHWmi:
- case X86::VPSHUFHWmi:
- case X86::VPSHUFHWYmi:
+ CASE_SHUF(PSHUFHW, mi)
DestName = getRegName(MI->getOperand(0).getReg());
if (MI->getOperand(NumOperands - 1).isImm())
DecodePSHUFHWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
@@ -388,14 +380,10 @@ bool llvm::EmitAnyX86InstComments(const
ShuffleMask);
break;
- case X86::PSHUFLWri:
- case X86::VPSHUFLWri:
- case X86::VPSHUFLWYri:
+ CASE_SHUF(PSHUFLW, ri)
Src1Name = getRegName(MI->getOperand(1).getReg());
// FALL THROUGH.
- case X86::PSHUFLWmi:
- case X86::VPSHUFLWmi:
- case X86::VPSHUFLWYmi:
+ CASE_SHUF(PSHUFLW, mi)
DestName = getRegName(MI->getOperand(0).getReg());
if (MI->getOperand(NumOperands - 1).isImm())
DecodePSHUFLWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
@@ -506,10 +494,10 @@ bool llvm::EmitAnyX86InstComments(const
DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
break;
- CASE_SHUF(SHUFPD, r)
+ CASE_SHUF(SHUFPD, rri)
Src2Name = getRegName(MI->getOperand(2).getReg());
// FALL THROUGH.
- CASE_SHUF(SHUFPD, m)
+ CASE_SHUF(SHUFPD, rmi)
if (MI->getOperand(NumOperands - 1).isImm())
DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0),
MI->getOperand(NumOperands - 1).getImm(),
@@ -518,10 +506,10 @@ bool llvm::EmitAnyX86InstComments(const
DestName = getRegName(MI->getOperand(0).getReg());
break;
- CASE_SHUF(SHUFPS, r)
+ CASE_SHUF(SHUFPS, rri)
Src2Name = getRegName(MI->getOperand(2).getReg());
// FALL THROUGH.
- CASE_SHUF(SHUFPS, m)
+ CASE_SHUF(SHUFPS, rmi)
if (MI->getOperand(NumOperands - 1).isImm())
DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0),
MI->getOperand(NumOperands - 1).getImm(),
Modified: llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll?rev=271628&r1=271627&r2=271628&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll Fri Jun 3 00:31:00 2016
@@ -6443,9 +6443,9 @@ define <16 x i32>@test_int_x86_avx512_ma
; CHECK-LABEL: test_int_x86_avx512_mask_pshuf_d_512:
; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %esi, %k1
-; CHECK-NEXT: vpshufd $3, %zmm0, %zmm1 {%k1}
-; CHECK-NEXT: vpshufd $3, %zmm0, %zmm2 {%k1} {z}
-; CHECK-NEXT: vpshufd $3, %zmm0, %zmm0
+; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm1[3,0,0,0,7,4,4,4,11,8,8,8,15,12,12,12]
+; CHECK-NEXT: vpshufd {{.*#+}} zmm2 = k1[3,0,0,0,7,4,4,4,11,8,8,8,15,12,12,12]
+; CHECK-NEXT: vpshufd {{.*#+}} zmm0 = zmm0[3,0,0,0,7,4,4,4,11,8,8,8,15,12,12,12]
; CHECK-NEXT: vpaddd %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll?rev=271628&r1=271627&r2=271628&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll Fri Jun 3 00:31:00 2016
@@ -5987,7 +5987,9 @@ define <8 x i16>@test_int_x86_avx512_mas
; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
; CHECK-NEXT: vpshufhw $3, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7e,0x09,0x70,0xc8,0x03]
+; CHECK-NEXT: ## xmm1 = xmm1[0,1,2,3,7,4,4,4]
; CHECK-NEXT: vpshufhw $3, %xmm0, %xmm2 {%k1} {z} ## encoding: [0x62,0xf1,0x7e,0x89,0x70,0xd0,0x03]
+; CHECK-NEXT: ## xmm2 = k1[0,1,2,3,7,4,4,4]
; CHECK-NEXT: vpshufhw $3, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x70,0xc0,0x03]
; CHECK-NEXT: ## xmm0 = xmm0[0,1,2,3,7,4,4,4]
; CHECK-NEXT: vpaddw %xmm2, %xmm1, %xmm1 ## encoding: [0x62,0xf1,0x75,0x08,0xfd,0xca]
@@ -6008,7 +6010,9 @@ define <16 x i16>@test_int_x86_avx512_ma
; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
; CHECK-NEXT: vpshufhw $3, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7e,0x29,0x70,0xc8,0x03]
+; CHECK-NEXT: ## ymm1 = ymm1[0,1,2,3,7,4,4,4,8,9,10,11,15,12,12,12]
; CHECK-NEXT: vpshufhw $3, %ymm0, %ymm2 {%k1} {z} ## encoding: [0x62,0xf1,0x7e,0xa9,0x70,0xd0,0x03]
+; CHECK-NEXT: ## ymm2 = k1[0,1,2,3,7,4,4,4,8,9,10,11,15,12,12,12]
; CHECK-NEXT: vpshufhw $3, %ymm0, %ymm0 ## encoding: [0xc5,0xfe,0x70,0xc0,0x03]
; CHECK-NEXT: ## ymm0 = ymm0[0,1,2,3,7,4,4,4,8,9,10,11,15,12,12,12]
; CHECK-NEXT: vpaddw %ymm2, %ymm1, %ymm1 ## encoding: [0x62,0xf1,0x75,0x28,0xfd,0xca]
@@ -6029,7 +6033,9 @@ define <8 x i16>@test_int_x86_avx512_mas
; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
; CHECK-NEXT: vpshuflw $3, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7f,0x09,0x70,0xc8,0x03]
+; CHECK-NEXT: ## xmm1 = xmm1[3,0,0,0,4,5,6,7]
; CHECK-NEXT: vpshuflw $3, %xmm0, %xmm2 {%k1} {z} ## encoding: [0x62,0xf1,0x7f,0x89,0x70,0xd0,0x03]
+; CHECK-NEXT: ## xmm2 = k1[3,0,0,0,4,5,6,7]
; CHECK-NEXT: vpshuflw $3, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x70,0xc0,0x03]
; CHECK-NEXT: ## xmm0 = xmm0[3,0,0,0,4,5,6,7]
; CHECK-NEXT: vpaddw %xmm2, %xmm1, %xmm1 ## encoding: [0x62,0xf1,0x75,0x08,0xfd,0xca]
@@ -6050,7 +6056,9 @@ define <16 x i16>@test_int_x86_avx512_ma
; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
; CHECK-NEXT: vpshuflw $3, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7f,0x29,0x70,0xc8,0x03]
+; CHECK-NEXT: ## ymm1 = ymm1[3,0,0,0,4,5,6,7,11,8,8,8,12,13,14,15]
; CHECK-NEXT: vpshuflw $3, %ymm0, %ymm2 {%k1} {z} ## encoding: [0x62,0xf1,0x7f,0xa9,0x70,0xd0,0x03]
+; CHECK-NEXT: ## ymm2 = k1[3,0,0,0,4,5,6,7,11,8,8,8,12,13,14,15]
; CHECK-NEXT: vpshuflw $3, %ymm0, %ymm0 ## encoding: [0xc5,0xff,0x70,0xc0,0x03]
; CHECK-NEXT: ## ymm0 = ymm0[3,0,0,0,4,5,6,7,11,8,8,8,12,13,14,15]
; CHECK-NEXT: vpaddw %ymm2, %ymm1, %ymm1 ## encoding: [0x62,0xf1,0x75,0x28,0xfd,0xca]
Modified: llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll?rev=271628&r1=271627&r2=271628&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll Fri Jun 3 00:31:00 2016
@@ -9552,7 +9552,9 @@ define <4 x i32>@test_int_x86_avx512_mas
; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
; CHECK-NEXT: vpshufd $3, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0x70,0xc8,0x03]
+; CHECK-NEXT: ## xmm1 = xmm1[3,0,0,0]
; CHECK-NEXT: vpshufd $3, %xmm0, %xmm2 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0x70,0xd0,0x03]
+; CHECK-NEXT: ## xmm2 = k1[3,0,0,0]
; CHECK-NEXT: vpshufd $3, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x70,0xc0,0x03]
; CHECK-NEXT: ## xmm0 = xmm0[3,0,0,0]
; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1 ## encoding: [0x62,0xf1,0x75,0x08,0xfe,0xca]
@@ -9573,7 +9575,9 @@ define <8 x i32>@test_int_x86_avx512_mas
; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
; CHECK-NEXT: vpshufd $3, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0x70,0xc8,0x03]
+; CHECK-NEXT: ## ymm1 = ymm1[3,0,0,0,7,4,4,4]
; CHECK-NEXT: vpshufd $3, %ymm0, %ymm2 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0x70,0xd0,0x03]
+; CHECK-NEXT: ## ymm2 = k1[3,0,0,0,7,4,4,4]
; CHECK-NEXT: vpshufd $3, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x70,0xc0,0x03]
; CHECK-NEXT: ## ymm0 = ymm0[3,0,0,0,7,4,4,4]
; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1 ## encoding: [0x62,0xf1,0x75,0x28,0xfe,0xca]
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