[llvm] r271356 - DAGCombiner: Fix broken size check in isAlias

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Tue May 31 18:00:40 PDT 2016


Author: arsenm
Date: Tue May 31 20:00:36 2016
New Revision: 271356

URL: http://llvm.org/viewvc/llvm-project?rev=271356&view=rev
Log:
DAGCombiner: Fix broken size check in isAlias

This should have been converting the size to bytes, but wasn't really.
These should probably all be using getStoreSize instead.

I haven't been able to come up with a meaningful testcase for this.
I can trigger it using combinations of struct loads and stores,
but can't observe a difference in non-broken testcases.

isAlias is only really used during store merging, so I'm not sure how
to get into the vector splitting situation the comment describes
since store merging is only done before type legalization.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=271356&r1=271355&r2=271356&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue May 31 20:00:36 2016
@@ -14731,7 +14731,7 @@ bool DAGCombiner::isAlias(LSBaseSDNode *
       (Op0->getSrcValueOffset() != Op1->getSrcValueOffset()) &&
       (Op0->getMemoryVT().getSizeInBits() >> 3 ==
        Op1->getMemoryVT().getSizeInBits() >> 3) &&
-      (Op0->getOriginalAlignment() > Op0->getMemoryVT().getSizeInBits()) >> 3) {
+      (Op0->getOriginalAlignment() > (Op0->getMemoryVT().getSizeInBits() >> 3))) {
     int64_t OffAlign1 = Op0->getSrcValueOffset() % Op0->getOriginalAlignment();
     int64_t OffAlign2 = Op1->getSrcValueOffset() % Op1->getOriginalAlignment();
 




More information about the llvm-commits mailing list