[PATCH] D20310: Teach LLVM about Power 9 D-Form VSX Instructions

[Hal Finkel via llvm-commits]

hfinkel added a comment.

In http://reviews.llvm.org/D20310#444384, @tjablin wrote:

> From CY:
>
> This patch prevent from defining new register class for vsx that uses 64-bit altivec register, it reuses VFRC register class, and does required changes when printing assembly code.
>
> VsxUseAltivecReg and VFRC are used in "PPCInstPrinter::printOperand", "PPCAsmPrinter::printOperand", in order to get correct register name for vsx that uses 64-bit altivec register.


Thanks for working on this. I'd really like to see a unified solution here, both for this and for the high half of the VSX register file in general (i.e. using this same scheme to eliminate the VSRH registers).

Also, although I suggested using the instruction flag bits for this, I think we should be able to do this without them by looking at the operand descriptions's register class:

  MI->getDesc().OpInfo[MO's index].RegClass == PPC::VFRCRegClassID


================
Comment at: lib/Target/PowerPC/PPCInstrFormats.td:41
@@ -40,1 +40,3 @@
 
+  /// Vsx instruction which uses altivec register
+  bits<1> VsxUseAltivecReg = 0;
----------------
Please spell VSX here in all caps (and in the flag name).


http://reviews.llvm.org/D20310