[PATCH] D20443: [PowerPC] - Combine loads of v4i8 to loads of i32 followed by bitcast

[Nemanja Ivanovic via llvm-commits]

nemanjai updated this revision to Diff 58968.
nemanjai added a comment.

This is a fundamentally different approach from the first attempt. As Ehsan suggested, I've updated how we legalize non-legal vector types. With this patch, if we do not support the vector type, we will widen it rather than performing an integer promotion which would often require scalarizing. However, widening can only be done when the bit-size of the vector element is a multiple of 8 (as we do not support any vectors made up of fractional byte elements).

There are instances where this approach produces worse code. This is exposed in some of the functions in the vsx.ll test case. To address one of those, this patch implements a DAG combine for a conversion of a v2i32 to v2f64 so that it remains a 2-instruction sequence. Similar DAG combines can later be implemented for other affected code patterns.


Repository:
  rL LLVM

http://reviews.llvm.org/D20443

Files:
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/PowerPC/PPCISelLowering.h
  lib/Target/PowerPC/PPCInstrVSX.td
  test/Analysis/CostModel/PowerPC/load_store.ll
  test/CodeGen/PowerPC/load-v4i8-improved.ll
  test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll
  test/CodeGen/PowerPC/vec_cmp.ll
  test/CodeGen/PowerPC/vsx.ll

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