[PATCH] D20627: Do not rename registers that do not start an independent live range

[Matthias Braun via llvm-commits]

MatzeB added a comment.

First: I have no experience with this pass and (independently of this patch) the code in this pass is complex and confusing...

It looks like you forbid renaming of schedule nodes if they have any earlier anti-,output- or data- dependencies of the same register. This seems overly conservative, shoulnd't you rather be checking that if you have a def of register R that all uses (data dep successors) only read R or a subregister but not a super-register of R?


================
Comment at: lib/CodeGen/AggressiveAntiDepBreaker.cpp:907-909
@@ +906,5 @@
+          // the larger register.
+          BitVector Aliases(TRI->getNumRegs());
+          for (MCRegAliasIterator AI(AntiDepReg, TRI, true); AI.isValid(); ++AI)
+            Aliases.set(*AI);
+          for (SDep S : PathSU->Succs) {
----------------
This seems expensive. I would at least move the `Aliases` variable out of the loop and simply clear it so the we do not need to allocate the memory again each iteration.

================
Comment at: lib/CodeGen/AggressiveAntiDepBreaker.cpp:917-918
@@ +916,4 @@
+              continue;
+            if (R == AntiDepReg || TRI->isSubRegister(AntiDepReg, R))
+              continue;
+            AntiDepReg = 0;
----------------
Isn't the `R == AntiDepReg || TRI->isSubRegister(AntiDepReg, R)` redundant after checking the Aliases bitset you construct here?


Repository:
  rL LLVM

http://reviews.llvm.org/D20627