[llvm] r270344 - [AVX512] Add a couple patterns to fix some cases where two vector mask inversions could appear in a row.

[Rafael Espíndola via llvm-commits]

Could this possibly have any impact on non avx-512 targets? We noticed
a regression with this in, but have not debugged it yet. The odd thing
is that the target cpu (jaguar) doesn't have avx-512.

Cheers,
Rafael


On 21 May 2016 at 20:39, Craig Topper via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: ctopper
> Date: Sat May 21 19:39:30 2016
> New Revision: 270344
>
> URL: http://llvm.org/viewvc/llvm-project?rev=270344&view=rev
> Log:
> [AVX512] Add a couple patterns to fix some cases where two vector mask inversions could appear in a row.
>
> Modified:
>     llvm/trunk/lib/Target/X86/X86InstrAVX512.td
>     llvm/trunk/test/CodeGen/X86/avx512-vec-cmp.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=270344&r1=270343&r2=270344&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Sat May 21 19:39:30 2016
> @@ -2761,6 +2761,17 @@ def : Pat<(v16i32 (vselect VK16WM:$mask,
>                             (v16i32 VR512:$src))),
>                    (VMOVDQA32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
>
> +// These patterns exist to prevent the above patterns from introducing a second
> +// mask inversion when one already exists.
> +def : Pat<(v8i64 (vselect (xor VK8:$mask, (v8i1 immAllOnesV)),
> +                          (bc_v8i64 (v16i32 immAllZerosV)),
> +                          (v8i64 VR512:$src))),
> +                 (VMOVDQA64Zrrkz VK8:$mask, VR512:$src)>;
> +def : Pat<(v16i32 (vselect (xor VK16:$mask, (v16i1 immAllOnesV)),
> +                           (v16i32 immAllZerosV),
> +                           (v16i32 VR512:$src))),
> +                  (VMOVDQA32Zrrkz VK16WM:$mask, VR512:$src)>;
> +
>  // Move Int Doubleword to Packed Double Int
>  //
>  def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
>
> Modified: llvm/trunk/test/CodeGen/X86/avx512-vec-cmp.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-vec-cmp.ll?rev=270344&r1=270343&r2=270344&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/avx512-vec-cmp.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/avx512-vec-cmp.ll Sat May 21 19:39:30 2016
> @@ -279,18 +279,14 @@ define <16 x i32> @test14(<16 x i32>%a,
>  ; KNL-LABEL: test14:
>  ; KNL:       ## BB#0:
>  ; KNL-NEXT:    vpsubd %zmm1, %zmm0, %zmm1
> -; KNL-NEXT:    vpcmpgtd %zmm0, %zmm1, %k0
> -; KNL-NEXT:    knotw %k0, %k0
> -; KNL-NEXT:    knotw %k0, %k1
> +; KNL-NEXT:    vpcmpgtd %zmm0, %zmm1, %k1
>  ; KNL-NEXT:    vmovdqa32 %zmm1, %zmm0 {%k1} {z}
>  ; KNL-NEXT:    retq
>  ;
>  ; SKX-LABEL: test14:
>  ; SKX:       ## BB#0:
>  ; SKX-NEXT:    vpsubd %zmm1, %zmm0, %zmm1
> -; SKX-NEXT:    vpcmpgtd %zmm0, %zmm1, %k0
> -; SKX-NEXT:    knotw %k0, %k0
> -; SKX-NEXT:    knotw %k0, %k1
> +; SKX-NEXT:    vpcmpgtd %zmm0, %zmm1, %k1
>  ; SKX-NEXT:    vmovdqa32 %zmm1, %zmm0 {%k1} {z}
>  ; SKX-NEXT:    retq
>    %sub_r = sub <16 x i32> %a, %b
> @@ -305,18 +301,14 @@ define <8 x i64> @test15(<8 x i64>%a, <8
>  ; KNL-LABEL: test15:
>  ; KNL:       ## BB#0:
>  ; KNL-NEXT:    vpsubq %zmm1, %zmm0, %zmm1
> -; KNL-NEXT:    vpcmpgtq %zmm0, %zmm1, %k0
> -; KNL-NEXT:    knotw %k0, %k0
> -; KNL-NEXT:    knotw %k0, %k1
> +; KNL-NEXT:    vpcmpgtq %zmm0, %zmm1, %k1
>  ; KNL-NEXT:    vmovdqa64 %zmm1, %zmm0 {%k1} {z}
>  ; KNL-NEXT:    retq
>  ;
>  ; SKX-LABEL: test15:
>  ; SKX:       ## BB#0:
>  ; SKX-NEXT:    vpsubq %zmm1, %zmm0, %zmm1
> -; SKX-NEXT:    vpcmpgtq %zmm0, %zmm1, %k0
> -; SKX-NEXT:    knotb %k0, %k0
> -; SKX-NEXT:    knotw %k0, %k1
> +; SKX-NEXT:    vpcmpgtq %zmm0, %zmm1, %k1
>  ; SKX-NEXT:    vmovdqa64 %zmm1, %zmm0 {%k1} {z}
>  ; SKX-NEXT:    retq
>    %sub_r = sub <8 x i64> %a, %b
>
>
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