[PATCH] D15779: [ELF] - Implemented optimization for R_X86_64_GOTPCREL relocation.

Rafael EspĂ­ndola via llvm-commits llvm-commits at lists.llvm.org
Tue May 24 13:21:16 PDT 2016

> Rafael, returning to this, I have few thoughts now.
> Latest x64 ABI describes 3 possible groups of relaxations atm (https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI):
> 1. Convert call and jump
> 2. Convert mov->lea
> 3. Convert Test and Binop Convert memory operand of test and binop into
> immediate operand, where binop is one of adc, add, and, cmp, or,
> sbb, sub, xor instructions, when position-independent code is disabled.
> If there was no 3, we probably would be able to leave R_RELAX_GOT_PC expression assigning
> logic as is and just teach relaxGot() to relax all of them at once. If do that at once, that would help to avoid
> the op code checks anywhere except relaxGot() itself.
> But 3 says that depending on PIC for a specific set of instruction relaxation is possible or not.
> That probably does not leave us a chance for above and solution I see is introduce Target method
> canGotBeRelaxed() or something, which will check the instructions opcodes, like:
>   bool canGotBeRelaxed() {
>   if (call or jump or move opcodes)
>     return true;
>   if (Test or given binop opcodes)
>     return !PIC:
>   return false; //I guess it is possible to have instructions that can not be relaxed even if RELX relaxation is present ?
>   }
> and call it from adjustExpr(). What do you think ?

Yes, I missed that case 3 is non pic only :-(

Given that we don't want to complicate the interface of getRelExpr, I
think that, relative to my patch, what is needed is

* Delete R_RELAXABLE_GOT_PC, getRelExpr returns just R_GOT_PC.
* In Writer.cpp, the code

   if (Expr == R_RELAXABLE_GOT_PC)


  if (Expr == R_GOT_PC && Target->canRelaxGot(....))

Given that we will need the predicate, I would leave this patch doing
just mov -> lea for now.


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