[llvm] r270334 - [AVX512] Add patterns for extracting subvectors and storing to memory.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat May 21 15:50:15 PDT 2016
Author: ctopper
Date: Sat May 21 17:50:14 2016
New Revision: 270334
URL: http://llvm.org/viewvc/llvm-project?rev=270334&view=rev
Log:
[AVX512] Add patterns for extracting subvectors and storing to memory.
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/test/CodeGen/X86/avx512-extract-subvector.ll
llvm/trunk/test/CodeGen/X86/masked_memop.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=270334&r1=270333&r2=270334&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Sat May 21 17:50:14 2016
@@ -656,17 +656,19 @@ multiclass vextract_for_size<int Opcode,
AVX512AIi8Base, EVEX;
let mayStore = 1 in {
def mr : AVX512AIi8<Opcode, MRMDestMem, (outs),
- (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$src2),
+ (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$idx),
"vextract" # To.EltTypeName # "x" # To.NumElts #
- "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
- []>, EVEX;
+ "\t{$idx, $src1, $dst|$dst, $src1, $idx}",
+ [(store (To.VT (vextract_extract:$idx
+ (From.VT From.RC:$src1), (iPTR imm))),
+ addr:$dst)]>, EVEX;
def mrk : AVX512AIi8<Opcode, MRMDestMem, (outs),
(ins To.MemOp:$dst, To.KRCWM:$mask,
- From.RC:$src1, i32u8imm:$src2),
+ From.RC:$src1, i32u8imm:$idx),
"vextract" # To.EltTypeName # "x" # To.NumElts #
- "\t{$src2, $src1, $dst {${mask}}|"
- "$dst {${mask}}, $src1, $src2}",
+ "\t{$idx, $src1, $dst {${mask}}|"
+ "$dst {${mask}}, $src1, $idx}",
[]>, EVEX_K, EVEX;
}//mayStore = 1
}
@@ -705,11 +707,16 @@ multiclass vextract_for_size_lowering<st
SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> :
vextract_for_size_first_position_lowering<From, To> {
- let Predicates = p in
+ let Predicates = p in {
def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
(To.VT (!cast<Instruction>(InstrStr#"rr")
From.RC:$src1,
(EXTRACT_get_vextract_imm To.RC:$ext)))>;
+ def : Pat<(store (To.VT (vextract_extract:$ext (From.VT From.RC:$src1),
+ (iPTR imm))), addr:$dst),
+ (!cast<Instruction>(InstrStr#"mr") addr:$dst, From.RC:$src1,
+ (EXTRACT_get_vextract_imm To.RC:$ext))>;
+ }
}
multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=270334&r1=270333&r2=270334&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sat May 21 17:50:14 2016
@@ -7946,7 +7946,7 @@ def VEXTRACTF128mr : AVXAIi8<0x19, MRMDe
}
// AVX1 patterns
-let Predicates = [HasAVX] in {
+let Predicates = [HasAVX, NoVLX] in {
def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
(v4f32 (VEXTRACTF128rr
(v8f32 VR256:$src1),
@@ -8634,9 +8634,7 @@ def : Pat<(vextract128_extract:$ext VR25
(v16i8 (VEXTRACTI128rr
(v32i8 VR256:$src1),
(EXTRACT_get_vextract128_imm VR128:$ext)))>;
-}
-let Predicates = [HasAVX2] in {
def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
(iPTR imm))), addr:$dst),
(VEXTRACTI128mr addr:$dst, VR256:$src1,
Modified: llvm/trunk/test/CodeGen/X86/avx512-extract-subvector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-extract-subvector.ll?rev=270334&r1=270333&r2=270334&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-extract-subvector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-extract-subvector.ll Sat May 21 17:50:14 2016
@@ -54,3 +54,75 @@ define <32 x i8> @extract_subvector256_v
%r1 = shufflevector <64 x i8> %x, <64 x i8> undef, <32 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
ret <32 x i8> %r1
}
+
+define void @extract_subvector256_v8f64_store(double* nocapture %addr, <4 x double> %a) nounwind uwtable ssp {
+; SKX-LABEL: extract_subvector256_v8f64_store:
+; SKX: ## BB#0: ## %entry
+; SKX-NEXT: vextractf64x2 $1, %ymm0, (%rdi)
+; SKX-NEXT: retq
+entry:
+ %0 = shufflevector <4 x double> %a, <4 x double> undef, <2 x i32> <i32 2, i32 3>
+ %1 = bitcast double* %addr to <2 x double>*
+ store <2 x double> %0, <2 x double>* %1, align 1
+ ret void
+}
+
+define void @extract_subvector256_v8f32_store(float* nocapture %addr, <8 x float> %a) nounwind uwtable ssp {
+; SKX-LABEL: extract_subvector256_v8f32_store:
+; SKX: ## BB#0: ## %entry
+; SKX-NEXT: vextractf32x4 $1, %ymm0, (%rdi)
+; SKX-NEXT: retq
+entry:
+ %0 = shufflevector <8 x float> %a, <8 x float> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %1 = bitcast float* %addr to <4 x float>*
+ store <4 x float> %0, <4 x float>* %1, align 1
+ ret void
+}
+
+define void @extract_subvector256_v4i64_store(i64* nocapture %addr, <4 x i64> %a) nounwind uwtable ssp {
+; SKX-LABEL: extract_subvector256_v4i64_store:
+; SKX: ## BB#0: ## %entry
+; SKX-NEXT: vextracti64x2 $1, %ymm0, (%rdi)
+; SKX-NEXT: retq
+entry:
+ %0 = shufflevector <4 x i64> %a, <4 x i64> undef, <2 x i32> <i32 2, i32 3>
+ %1 = bitcast i64* %addr to <2 x i64>*
+ store <2 x i64> %0, <2 x i64>* %1, align 1
+ ret void
+}
+
+define void @extract_subvector256_v8i32_store(i32* nocapture %addr, <8 x i32> %a) nounwind uwtable ssp {
+; SKX-LABEL: extract_subvector256_v8i32_store:
+; SKX: ## BB#0: ## %entry
+; SKX-NEXT: vextracti32x4 $1, %ymm0, (%rdi)
+; SKX-NEXT: retq
+entry:
+ %0 = shufflevector <8 x i32> %a, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %1 = bitcast i32* %addr to <4 x i32>*
+ store <4 x i32> %0, <4 x i32>* %1, align 1
+ ret void
+}
+
+define void @extract_subvector256_v16i16_store(i16* nocapture %addr, <16 x i16> %a) nounwind uwtable ssp {
+; SKX-LABEL: extract_subvector256_v16i16_store:
+; SKX: ## BB#0: ## %entry
+; SKX-NEXT: vextracti32x4 $1, %ymm0, (%rdi)
+; SKX-NEXT: retq
+entry:
+ %0 = shufflevector <16 x i16> %a, <16 x i16> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %1 = bitcast i16* %addr to <8 x i16>*
+ store <8 x i16> %0, <8 x i16>* %1, align 1
+ ret void
+}
+
+define void @extract_subvector256_v32i8_store(i8* nocapture %addr, <32 x i8> %a) nounwind uwtable ssp {
+; SKX-LABEL: extract_subvector256_v32i8_store:
+; SKX: ## BB#0: ## %entry
+; SKX-NEXT: vextracti32x4 $1, %ymm0, (%rdi)
+; SKX-NEXT: retq
+entry:
+ %0 = shufflevector <32 x i8> %a, <32 x i8> undef, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+ %1 = bitcast i8* %addr to <16 x i8>*
+ store <16 x i8> %0, <16 x i8>* %1, align 1
+ ret void
+}
Modified: llvm/trunk/test/CodeGen/X86/masked_memop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/masked_memop.ll?rev=270334&r1=270333&r2=270334&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/masked_memop.ll (original)
+++ llvm/trunk/test/CodeGen/X86/masked_memop.ll Sat May 21 17:50:14 2016
@@ -1274,11 +1274,17 @@ define void @one_mask_bit_set4(<4 x doub
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
;
-; AVX512-LABEL: one_mask_bit_set4:
-; AVX512: ## BB#0:
-; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm0
-; AVX512-NEXT: vmovhpd %xmm0, 24(%rdi)
-; AVX512-NEXT: retq
+; AVX512F-LABEL: one_mask_bit_set4:
+; AVX512F: ## BB#0:
+; AVX512F-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX512F-NEXT: vmovhpd %xmm0, 24(%rdi)
+; AVX512F-NEXT: retq
+;
+; SKX-LABEL: one_mask_bit_set4:
+; SKX: ## BB#0:
+; SKX-NEXT: vextractf32x4 $1, %ymm0, %xmm0
+; SKX-NEXT: vmovhpd %xmm0, 24(%rdi)
+; SKX-NEXT: retq
call void @llvm.masked.store.v4f64(<4 x double> %val, <4 x double>* %addr, i32 4, <4 x i1><i1 false, i1 false, i1 false, i1 true>)
ret void
}
@@ -1387,7 +1393,7 @@ define <4 x double> @load_one_mask_bit_s
;
; SKX-LABEL: load_one_mask_bit_set4:
; SKX: ## BB#0:
-; SKX-NEXT: vextractf128 $1, %ymm0, %xmm1
+; SKX-NEXT: vextractf32x4 $1, %ymm0, %xmm1
; SKX-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0]
; SKX-NEXT: vinsertf32x4 $1, %xmm1, %ymm0, %ymm0
; SKX-NEXT: retq
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