[PATCH] D20310: Teach LLVM about Power 9 D-Form VSX Instructions

[Nemanja Ivanovic via llvm-commits]

nemanjai added a comment.

In http://reviews.llvm.org/D20310#435420, @cycheng wrote:

> In http://reviews.llvm.org/D20310#432000, @nemanjai wrote:
>
> > This is going to need some additional work to restrict the register sets for all the instructions. Of course, these are scalar loads/stores but they're restricted to the upper 32 VSX registers (the VMX registers) so we can't use the full vsfrc/vssrc register classes.
>
>
> I missed Nemanjai's comment, I did some test and looks like we can use vfrc register calss instead:


Unfortunately, this still isn't quite the correct semantics. Although this will target the right physical registers, the encoding is wrong. These really are VR registers and have 5-bit fields in the encoding. Things like:

  lxsd 35, 8(3)

are not likely to produce the desired results. These instructions need the VR register to be specified in the 0-31 range which will actually mean VSR 32-63.
As far as I can tell, the idea with these instructions is that we get scalar floating point values using the nice D-Form loads into the remaining VSR's (the FP D-Form loads can be used for VSRs 0-31).

I think perhaps the best way to handle these would be to define a new register class which will alias the VRRC registers, but has 64-bit spill size and can hold f64/f32.


http://reviews.llvm.org/D20310