[PATCH] D19428: AMDGPU: Define priorities for register classes

Matthias Braun via llvm-commits llvm-commits at lists.llvm.org
Wed May 18 18:23:10 PDT 2016


MatzeB added inline comments.

================
Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:278-280
@@ -267,5 +277,5 @@
 def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add TTMP_64Regs)> {
   let isAllocatable = 0;
 }
 
 def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
----------------
No. Priorities only affect the order in which liveintervals are allocated. By nature we will not allocate non-allocatable classes, so this was unnecessary.


http://reviews.llvm.org/D19428





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