[llvm] r269930 - [WebAssembly] Don't expand divisions by constants.

Dan Gohman via llvm-commits llvm-commits at lists.llvm.org
Wed May 18 07:29:42 PDT 2016


Author: djg
Date: Wed May 18 09:29:42 2016
New Revision: 269930

URL: http://llvm.org/viewvc/llvm-project?rev=269930&view=rev
Log:
[WebAssembly] Don't expand divisions by constants.

Don't expand divisions by constants if it would require multiple instructions.
The current assumption is that engines will perform the desired optimizations.

Added:
    llvm/trunk/test/CodeGen/WebAssembly/divrem-constant.ll
Modified:
    llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
    llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h

Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp?rev=269930&r1=269929&r2=269930&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp Wed May 18 09:29:42 2016
@@ -243,6 +243,12 @@ bool WebAssemblyTargetLowering::allowsMi
   return true;
 }
 
+bool WebAssemblyTargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
+  // The current thinking is that wasm engines will perform this optimization,
+  // so we can save on code size.
+  return true;
+}
+
 //===----------------------------------------------------------------------===//
 // WebAssembly Lowering private implementation.
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h?rev=269930&r1=269929&r2=269930&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h Wed May 18 09:29:42 2016
@@ -58,6 +58,7 @@ class WebAssemblyTargetLowering final :
                              unsigned AS) const override;
   bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace, unsigned Align,
                                       bool *Fast) const override;
+  bool isIntDivCheap(EVT VT, AttributeSet Attr) const override;
 
   SDValue LowerCall(CallLoweringInfo &CLI,
                     SmallVectorImpl<SDValue> &InVals) const override;

Added: llvm/trunk/test/CodeGen/WebAssembly/divrem-constant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/divrem-constant.ll?rev=269930&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/divrem-constant.ll (added)
+++ llvm/trunk/test/CodeGen/WebAssembly/divrem-constant.ll Wed May 18 09:29:42 2016
@@ -0,0 +1,62 @@
+; RUN: llc < %s -asm-verbose=false | FileCheck %s
+
+; Test that integer div and rem by constant are optimized appropriately.
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown"
+
+; CHECK-LABEL: test_udiv_2:
+; CHECK: i32.shr_u
+define i32 @test_udiv_2(i32 %x) {
+    %t = udiv i32 %x, 2
+    ret i32 %t
+}
+
+; CHECK-LABEL: test_udiv_5:
+; CHECK: i32.div_u
+define i32 @test_udiv_5(i32 %x) {
+    %t = udiv i32 %x, 5
+    ret i32 %t
+}
+
+; CHECK-LABEL: test_sdiv_2:
+; CHECK: i32.div_s
+define i32 @test_sdiv_2(i32 %x) {
+    %t = sdiv i32 %x, 2
+    ret i32 %t
+}
+
+; CHECK-LABEL: test_sdiv_5:
+; CHECK: i32.div_s
+define i32 @test_sdiv_5(i32 %x) {
+    %t = sdiv i32 %x, 5
+    ret i32 %t
+}
+
+; CHECK-LABEL: test_urem_2:
+; CHECK: i32.and
+define i32 @test_urem_2(i32 %x) {
+    %t = urem i32 %x, 2
+    ret i32 %t
+}
+
+; CHECK-LABEL: test_urem_5:
+; CHECK: i32.rem_u
+define i32 @test_urem_5(i32 %x) {
+    %t = urem i32 %x, 5
+    ret i32 %t
+}
+
+; CHECK-LABEL: test_srem_2:
+; CHECK: i32.rem_s
+define i32 @test_srem_2(i32 %x) {
+    %t = srem i32 %x, 2
+    ret i32 %t
+}
+
+; CHECK-LABEL: test_srem_5:
+; CHECK: i32.rem_s
+define i32 @test_srem_5(i32 %x) {
+    %t = srem i32 %x, 5
+    ret i32 %t
+}




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