[PATCH] D20295: When looking for a spill slot in reg scavenger, find one that matches RC

[Krzysztof Parzyszek via llvm-commits]

kparzysz added inline comments.

================
Comment at: lib/CodeGen/RegisterScavenging.cpp:414
@@ +413,3 @@
+    // that is the best fit for this register class (in street metric).
+    unsigned D = (S-NeedSize) + (A-NeedAlign);
+    if (D < Diff) {
----------------
qcolombet wrote:
> Did you actually see cases where we should care?
> 
> I would rather return the first matching one and be done with the loop.
On Hexagon we can reserve spill slots for vectors (64-byte size/alignment) and integer registers (4/8-byte size/alignment).  I'm concerned that depending on the order of reservation we can end up using a vector slot for an integer register.

================
Comment at: lib/CodeGen/RegisterScavenging.cpp:439
@@ -415,1 +438,3 @@
+      llvm_unreachable(
            "Cannot scavenge register without an emergency spill slot!");
+    }
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qcolombet wrote:
> Given that we saw it can happen, I would go with a report_fatal_error.
Will do.

================
Comment at: test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll:106
@@ +105,3 @@
+  %niter.ncmp.7 = icmp eq i32 %niter.nsub.7, 0
+  br i1 %niter.ncmp.7, label %for.end.loopexit.unr-lcssa, label %for.body
+
----------------
qcolombet wrote:
> Could you make the test smaller, e.g., via using inline asm to clobber registers?
> (You could also use mir input.)
Let me see what I can do with inline asm.  I haven't tried MIR with our backend so I'm not sure how much work it will be to get it to work.


Repository:
  rL LLVM

http://reviews.llvm.org/D20295