[llvm] r269483 - SDAG: Implement Select instead of SelectImpl in NVPTXDAGToDAGISel
Justin Bogner via llvm-commits
llvm-commits at lists.llvm.org
Fri May 13 14:12:53 PDT 2016
Author: bogner
Date: Fri May 13 16:12:53 2016
New Revision: 269483
URL: http://llvm.org/viewvc/llvm-project?rev=269483&view=rev
Log:
SDAG: Implement Select instead of SelectImpl in NVPTXDAGToDAGISel
- Where we were returning a node before, call ReplaceNode instead.
- Where we would return null to fall back to another selector, rename
the method to try* and return a bool for success.
Part of llvm.org/pr26808.
Modified:
llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp?rev=269483&r1=269482&r2=269483&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp Fri May 13 16:12:53 2016
@@ -105,57 +105,66 @@ bool NVPTXDAGToDAGISel::allowFMA() const
/// Select - Select instructions not customized! Used for
/// expanded, promoted and normal instructions.
-SDNode *NVPTXDAGToDAGISel::SelectImpl(SDNode *N) {
+void NVPTXDAGToDAGISel::Select(SDNode *N) {
if (N->isMachineOpcode()) {
N->setNodeId(-1);
- return nullptr; // Already selected.
+ return; // Already selected.
}
- SDNode *ResNode = nullptr;
switch (N->getOpcode()) {
case ISD::LOAD:
- ResNode = SelectLoad(N);
+ if (tryLoad(N))
+ return;
break;
case ISD::STORE:
- ResNode = SelectStore(N);
+ if (tryStore(N))
+ return;
break;
case NVPTXISD::LoadV2:
case NVPTXISD::LoadV4:
- ResNode = SelectLoadVector(N);
+ if (tryLoadVector(N))
+ return;
break;
case NVPTXISD::LDGV2:
case NVPTXISD::LDGV4:
case NVPTXISD::LDUV2:
case NVPTXISD::LDUV4:
- ResNode = SelectLDGLDU(N);
+ if (tryLDGLDU(N))
+ return;
break;
case NVPTXISD::StoreV2:
case NVPTXISD::StoreV4:
- ResNode = SelectStoreVector(N);
+ if (tryStoreVector(N))
+ return;
break;
case NVPTXISD::LoadParam:
case NVPTXISD::LoadParamV2:
case NVPTXISD::LoadParamV4:
- ResNode = SelectLoadParam(N);
+ if (tryLoadParam(N))
+ return;
break;
case NVPTXISD::StoreRetval:
case NVPTXISD::StoreRetvalV2:
case NVPTXISD::StoreRetvalV4:
- ResNode = SelectStoreRetval(N);
+ if (tryStoreRetval(N))
+ return;
break;
case NVPTXISD::StoreParam:
case NVPTXISD::StoreParamV2:
case NVPTXISD::StoreParamV4:
case NVPTXISD::StoreParamS32:
case NVPTXISD::StoreParamU32:
- ResNode = SelectStoreParam(N);
+ if (tryStoreParam(N))
+ return;
break;
case ISD::INTRINSIC_WO_CHAIN:
- ResNode = SelectIntrinsicNoChain(N);
+ if (tryIntrinsicNoChain(N))
+ return;
break;
case ISD::INTRINSIC_W_CHAIN:
- ResNode = SelectIntrinsicChain(N);
+ if (tryIntrinsicChain(N))
+ return;
break;
case NVPTXISD::Tex1DFloatS32:
case NVPTXISD::Tex1DFloatFloat:
@@ -325,7 +334,8 @@ SDNode *NVPTXDAGToDAGISel::SelectImpl(SD
case NVPTXISD::Tld4UnifiedG2DU64Float:
case NVPTXISD::Tld4UnifiedB2DU64Float:
case NVPTXISD::Tld4UnifiedA2DU64Float:
- ResNode = SelectTextureIntrinsic(N);
+ if (tryTextureIntrinsic(N))
+ return;
break;
case NVPTXISD::Suld1DI8Clamp:
case NVPTXISD::Suld1DI16Clamp:
@@ -492,37 +502,37 @@ SDNode *NVPTXDAGToDAGISel::SelectImpl(SD
case NVPTXISD::Suld3DV4I8Zero:
case NVPTXISD::Suld3DV4I16Zero:
case NVPTXISD::Suld3DV4I32Zero:
- ResNode = SelectSurfaceIntrinsic(N);
+ if (trySurfaceIntrinsic(N))
+ return;
break;
case ISD::AND:
case ISD::SRA:
case ISD::SRL:
// Try to select BFE
- ResNode = SelectBFE(N);
+ if (tryBFE(N))
+ return;
break;
case ISD::ADDRSPACECAST:
- ResNode = SelectAddrSpaceCast(N);
- break;
+ SelectAddrSpaceCast(N);
+ return;
default:
break;
}
- if (ResNode)
- return ResNode;
- return SelectCode(N);
+ SelectCode(N);
}
-SDNode *NVPTXDAGToDAGISel::SelectIntrinsicChain(SDNode *N) {
+bool NVPTXDAGToDAGISel::tryIntrinsicChain(SDNode *N) {
unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
switch (IID) {
default:
- return NULL;
+ return false;
case Intrinsic::nvvm_ldg_global_f:
case Intrinsic::nvvm_ldg_global_i:
case Intrinsic::nvvm_ldg_global_p:
case Intrinsic::nvvm_ldu_global_f:
case Intrinsic::nvvm_ldu_global_i:
case Intrinsic::nvvm_ldu_global_p:
- return SelectLDGLDU(N);
+ return tryLDGLDU(N);
}
}
@@ -579,25 +589,26 @@ static bool canLowerToLDG(MemSDNode *N,
return true;
}
-SDNode *NVPTXDAGToDAGISel::SelectIntrinsicNoChain(SDNode *N) {
+bool NVPTXDAGToDAGISel::tryIntrinsicNoChain(SDNode *N) {
unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
switch (IID) {
default:
- return nullptr;
+ return false;
case Intrinsic::nvvm_texsurf_handle_internal:
- return SelectTexSurfHandle(N);
+ SelectTexSurfHandle(N);
+ return true;
}
}
-SDNode *NVPTXDAGToDAGISel::SelectTexSurfHandle(SDNode *N) {
+void NVPTXDAGToDAGISel::SelectTexSurfHandle(SDNode *N) {
// Op 0 is the intrinsic ID
SDValue Wrapper = N->getOperand(1);
SDValue GlobalVal = Wrapper.getOperand(0);
- return CurDAG->getMachineNode(NVPTX::texsurf_handles, SDLoc(N), MVT::i64,
- GlobalVal);
+ ReplaceNode(N, CurDAG->getMachineNode(NVPTX::texsurf_handles, SDLoc(N),
+ MVT::i64, GlobalVal));
}
-SDNode *NVPTXDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
+void NVPTXDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
SDValue Src = N->getOperand(0);
AddrSpaceCastSDNode *CastN = cast<AddrSpaceCastSDNode>(N);
unsigned SrcAddrSpace = CastN->getSrcAddressSpace();
@@ -624,7 +635,9 @@ SDNode *NVPTXDAGToDAGISel::SelectAddrSpa
Opc = TM.is64Bit() ? NVPTX::cvta_local_yes_64 : NVPTX::cvta_local_yes;
break;
}
- return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
+ ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0),
+ Src));
+ return;
} else {
// Generic to specific
if (SrcAddrSpace != 0)
@@ -653,11 +666,13 @@ SDNode *NVPTXDAGToDAGISel::SelectAddrSpa
: NVPTX::nvvm_ptr_gen_to_param;
break;
}
- return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
+ ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0),
+ Src));
+ return;
}
}
-SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
+bool NVPTXDAGToDAGISel::tryLoad(SDNode *N) {
SDLoc dl(N);
LoadSDNode *LD = cast<LoadSDNode>(N);
EVT LoadedVT = LD->getMemoryVT();
@@ -665,16 +680,16 @@ SDNode *NVPTXDAGToDAGISel::SelectLoad(SD
// do not support pre/post inc/dec
if (LD->isIndexed())
- return nullptr;
+ return false;
if (!LoadedVT.isSimple())
- return nullptr;
+ return false;
// Address Space Setting
unsigned int codeAddrSpace = getCodeAddrSpace(LD);
if (canLowerToLDG(LD, *Subtarget, codeAddrSpace, MF)) {
- return SelectLDGLDU(N);
+ return tryLDGLDU(N);
}
// Volatile Setting
@@ -695,7 +710,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoad(SD
else if (num == 4)
vecType = NVPTX::PTXLdStInstCode::V4;
else
- return nullptr;
+ return false;
}
// Type Setting: fromType + fromTypeWidth
@@ -744,7 +759,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoad(SD
Opcode = NVPTX::LD_f64_avar;
break;
default:
- return nullptr;
+ return false;
}
SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
getI32Imm(vecType, dl), getI32Imm(fromType, dl),
@@ -772,7 +787,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoad(SD
Opcode = NVPTX::LD_f64_asi;
break;
default:
- return nullptr;
+ return false;
}
SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
getI32Imm(vecType, dl), getI32Imm(fromType, dl),
@@ -801,7 +816,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoad(SD
Opcode = NVPTX::LD_f64_ari_64;
break;
default:
- return nullptr;
+ return false;
}
} else {
switch (TargetVT) {
@@ -824,7 +839,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoad(SD
Opcode = NVPTX::LD_f64_ari;
break;
default:
- return nullptr;
+ return false;
}
}
SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
@@ -853,7 +868,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoad(SD
Opcode = NVPTX::LD_f64_areg_64;
break;
default:
- return nullptr;
+ return false;
}
} else {
switch (TargetVT) {
@@ -876,7 +891,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoad(SD
Opcode = NVPTX::LD_f64_areg;
break;
default:
- return nullptr;
+ return false;
}
}
SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
@@ -885,16 +900,18 @@ SDNode *NVPTXDAGToDAGISel::SelectLoad(SD
NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
}
- if (NVPTXLD) {
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- cast<MachineSDNode>(NVPTXLD)->setMemRefs(MemRefs0, MemRefs0 + 1);
- }
+ if (!NVPTXLD)
+ return false;
+
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ cast<MachineSDNode>(NVPTXLD)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return NVPTXLD;
+ ReplaceNode(N, NVPTXLD);
+ return true;
}
-SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) {
+bool NVPTXDAGToDAGISel::tryLoadVector(SDNode *N) {
SDValue Chain = N->getOperand(0);
SDValue Op1 = N->getOperand(1);
@@ -906,13 +923,13 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVec
EVT LoadedVT = MemSD->getMemoryVT();
if (!LoadedVT.isSimple())
- return nullptr;
+ return false;
// Address Space Setting
unsigned int CodeAddrSpace = getCodeAddrSpace(MemSD);
if (canLowerToLDG(MemSD, *Subtarget, CodeAddrSpace, MF)) {
- return SelectLDGLDU(N);
+ return tryLDGLDU(N);
}
// Volatile Setting
@@ -956,7 +973,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVec
VecType = NVPTX::PTXLdStInstCode::V4;
break;
default:
- return nullptr;
+ return false;
}
EVT EltVT = N->getValueType(0);
@@ -964,11 +981,11 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVec
if (SelectDirectAddr(Op1, Addr)) {
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case NVPTXISD::LoadV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::LDV_i8_v2_avar;
break;
@@ -992,7 +1009,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVec
case NVPTXISD::LoadV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::LDV_i8_v4_avar;
break;
@@ -1017,11 +1034,11 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVec
: SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) {
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case NVPTXISD::LoadV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::LDV_i8_v2_asi;
break;
@@ -1045,7 +1062,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVec
case NVPTXISD::LoadV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::LDV_i8_v4_asi;
break;
@@ -1071,11 +1088,11 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVec
if (TM.is64Bit()) {
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case NVPTXISD::LoadV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::LDV_i8_v2_ari_64;
break;
@@ -1099,7 +1116,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVec
case NVPTXISD::LoadV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::LDV_i8_v4_ari_64;
break;
@@ -1118,11 +1135,11 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVec
} else {
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case NVPTXISD::LoadV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::LDV_i8_v2_ari;
break;
@@ -1146,7 +1163,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVec
case NVPTXISD::LoadV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::LDV_i8_v4_ari;
break;
@@ -1173,11 +1190,11 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVec
if (TM.is64Bit()) {
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case NVPTXISD::LoadV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::LDV_i8_v2_areg_64;
break;
@@ -1201,7 +1218,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVec
case NVPTXISD::LoadV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::LDV_i8_v4_areg_64;
break;
@@ -1220,11 +1237,11 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVec
} else {
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case NVPTXISD::LoadV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::LDV_i8_v2_areg;
break;
@@ -1248,7 +1265,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVec
case NVPTXISD::LoadV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::LDV_i8_v4_areg;
break;
@@ -1276,10 +1293,11 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVec
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return LD;
+ ReplaceNode(N, LD);
+ return true;
}
-SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(SDNode *N) {
+bool NVPTXDAGToDAGISel::tryLDGLDU(SDNode *N) {
SDValue Chain = N->getOperand(0);
SDValue Op1;
@@ -1294,7 +1312,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
switch (IID) {
default:
- return NULL;
+ return false;
case Intrinsic::nvvm_ldg_global_f:
case Intrinsic::nvvm_ldg_global_i:
case Intrinsic::nvvm_ldg_global_p:
@@ -1337,12 +1355,12 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
if (SelectDirectAddr(Op1, Addr)) {
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case ISD::INTRINSIC_W_CHAIN:
if (IsLDG) {
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8avar;
break;
@@ -1365,7 +1383,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
} else {
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8avar;
break;
@@ -1390,7 +1408,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDGV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_avar;
break;
@@ -1414,7 +1432,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDUV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_avar;
break;
@@ -1438,7 +1456,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDGV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_avar;
break;
@@ -1456,7 +1474,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDUV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_avar;
break;
@@ -1480,13 +1498,13 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
if (TM.is64Bit()) {
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case ISD::LOAD:
case ISD::INTRINSIC_W_CHAIN:
if (IsLDG) {
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8ari64;
break;
@@ -1509,7 +1527,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
} else {
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8ari64;
break;
@@ -1535,7 +1553,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDGV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari64;
break;
@@ -1559,7 +1577,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDUV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari64;
break;
@@ -1584,7 +1602,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDGV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari64;
break;
@@ -1602,7 +1620,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDUV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari64;
break;
@@ -1621,13 +1639,13 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
} else {
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case ISD::LOAD:
case ISD::INTRINSIC_W_CHAIN:
if (IsLDG) {
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8ari;
break;
@@ -1650,7 +1668,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
} else {
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8ari;
break;
@@ -1676,7 +1694,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDGV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari32;
break;
@@ -1700,7 +1718,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDUV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari32;
break;
@@ -1725,7 +1743,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDGV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari32;
break;
@@ -1743,7 +1761,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDUV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari32;
break;
@@ -1768,13 +1786,13 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
if (TM.is64Bit()) {
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case ISD::LOAD:
case ISD::INTRINSIC_W_CHAIN:
if (IsLDG) {
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8areg64;
break;
@@ -1797,7 +1815,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
} else {
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8areg64;
break;
@@ -1823,7 +1841,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDGV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg64;
break;
@@ -1847,7 +1865,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDUV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg64;
break;
@@ -1872,7 +1890,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDGV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg64;
break;
@@ -1890,7 +1908,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDUV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg64;
break;
@@ -1909,13 +1927,13 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
} else {
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case ISD::LOAD:
case ISD::INTRINSIC_W_CHAIN:
if (IsLDG) {
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8areg;
break;
@@ -1938,7 +1956,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
} else {
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8areg;
break;
@@ -1964,7 +1982,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDGV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg32;
break;
@@ -1988,7 +2006,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDUV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg32;
break;
@@ -2013,7 +2031,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDGV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg32;
break;
@@ -2031,7 +2049,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
case NVPTXISD::LDUV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg32;
break;
@@ -2093,10 +2111,11 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(
}
}
- return LD;
+ ReplaceNode(N, LD);
+ return true;
}
-SDNode *NVPTXDAGToDAGISel::SelectStore(SDNode *N) {
+bool NVPTXDAGToDAGISel::tryStore(SDNode *N) {
SDLoc dl(N);
StoreSDNode *ST = cast<StoreSDNode>(N);
EVT StoreVT = ST->getMemoryVT();
@@ -2104,10 +2123,10 @@ SDNode *NVPTXDAGToDAGISel::SelectStore(S
// do not support pre/post inc/dec
if (ST->isIndexed())
- return nullptr;
+ return false;
if (!StoreVT.isSimple())
- return nullptr;
+ return false;
// Address Space Setting
unsigned int codeAddrSpace = getCodeAddrSpace(ST);
@@ -2130,7 +2149,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStore(S
else if (num == 4)
vecType = NVPTX::PTXLdStInstCode::V4;
else
- return nullptr;
+ return false;
}
// Type Setting: toType + toTypeWidth
@@ -2174,7 +2193,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStore(S
Opcode = NVPTX::ST_f64_avar;
break;
default:
- return nullptr;
+ return false;
}
SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
@@ -2203,7 +2222,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStore(S
Opcode = NVPTX::ST_f64_asi;
break;
default:
- return nullptr;
+ return false;
}
SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
@@ -2233,7 +2252,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStore(S
Opcode = NVPTX::ST_f64_ari_64;
break;
default:
- return nullptr;
+ return false;
}
} else {
switch (SourceVT) {
@@ -2256,7 +2275,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStore(S
Opcode = NVPTX::ST_f64_ari;
break;
default:
- return nullptr;
+ return false;
}
}
SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
@@ -2286,7 +2305,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStore(S
Opcode = NVPTX::ST_f64_areg_64;
break;
default:
- return nullptr;
+ return false;
}
} else {
switch (SourceVT) {
@@ -2309,7 +2328,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStore(S
Opcode = NVPTX::ST_f64_areg;
break;
default:
- return nullptr;
+ return false;
}
}
SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
@@ -2319,16 +2338,17 @@ SDNode *NVPTXDAGToDAGISel::SelectStore(S
NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
}
- if (NVPTXST) {
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- cast<MachineSDNode>(NVPTXST)->setMemRefs(MemRefs0, MemRefs0 + 1);
- }
+ if (!NVPTXST)
+ return false;
- return NVPTXST;
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ cast<MachineSDNode>(NVPTXST)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceNode(N, NVPTXST);
+ return true;
}
-SDNode *NVPTXDAGToDAGISel::SelectStoreVector(SDNode *N) {
+bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
SDValue Chain = N->getOperand(0);
SDValue Op1 = N->getOperand(1);
SDValue Addr, Offset, Base;
@@ -2386,7 +2406,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreVe
N2 = N->getOperand(5);
break;
default:
- return nullptr;
+ return false;
}
StOps.push_back(getI32Imm(IsVolatile, DL));
@@ -2398,11 +2418,11 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreVe
if (SelectDirectAddr(N2, Addr)) {
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case NVPTXISD::StoreV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::STV_i8_v2_avar;
break;
@@ -2426,7 +2446,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreVe
case NVPTXISD::StoreV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::STV_i8_v4_avar;
break;
@@ -2447,11 +2467,11 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreVe
: SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case NVPTXISD::StoreV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::STV_i8_v2_asi;
break;
@@ -2475,7 +2495,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreVe
case NVPTXISD::StoreV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::STV_i8_v4_asi;
break;
@@ -2498,11 +2518,11 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreVe
if (TM.is64Bit()) {
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case NVPTXISD::StoreV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::STV_i8_v2_ari_64;
break;
@@ -2526,7 +2546,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreVe
case NVPTXISD::StoreV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::STV_i8_v4_ari_64;
break;
@@ -2545,11 +2565,11 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreVe
} else {
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case NVPTXISD::StoreV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::STV_i8_v2_ari;
break;
@@ -2573,7 +2593,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreVe
case NVPTXISD::StoreV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::STV_i8_v4_ari;
break;
@@ -2596,11 +2616,11 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreVe
if (TM.is64Bit()) {
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case NVPTXISD::StoreV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::STV_i8_v2_areg_64;
break;
@@ -2624,7 +2644,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreVe
case NVPTXISD::StoreV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::STV_i8_v4_areg_64;
break;
@@ -2643,11 +2663,11 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreVe
} else {
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case NVPTXISD::StoreV2:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::STV_i8_v2_areg;
break;
@@ -2671,7 +2691,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreVe
case NVPTXISD::StoreV4:
switch (EltVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i8:
Opcode = NVPTX::STV_i8_v4_areg;
break;
@@ -2699,10 +2719,11 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreVe
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
cast<MachineSDNode>(ST)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ST;
+ ReplaceNode(N, ST);
+ return true;
}
-SDNode *NVPTXDAGToDAGISel::SelectLoadParam(SDNode *Node) {
+bool NVPTXDAGToDAGISel::tryLoadParam(SDNode *Node) {
SDValue Chain = Node->getOperand(0);
SDValue Offset = Node->getOperand(2);
SDValue Flag = Node->getOperand(3);
@@ -2712,7 +2733,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadPar
unsigned VecSize;
switch (Node->getOpcode()) {
default:
- return nullptr;
+ return false;
case NVPTXISD::LoadParam:
VecSize = 1;
break;
@@ -2731,11 +2752,11 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadPar
switch (VecSize) {
default:
- return nullptr;
+ return false;
case 1:
switch (MemVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i1:
Opc = NVPTX::LoadParamMemI8;
break;
@@ -2762,7 +2783,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadPar
case 2:
switch (MemVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i1:
Opc = NVPTX::LoadParamMemV2I8;
break;
@@ -2789,7 +2810,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadPar
case 4:
switch (MemVT.getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i1:
Opc = NVPTX::LoadParamMemV4I8;
break;
@@ -2826,10 +2847,11 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadPar
Ops.push_back(Chain);
Ops.push_back(Flag);
- return CurDAG->getMachineNode(Opc, DL, VTs, Ops);
+ ReplaceNode(Node, CurDAG->getMachineNode(Opc, DL, VTs, Ops));
+ return true;
}
-SDNode *NVPTXDAGToDAGISel::SelectStoreRetval(SDNode *N) {
+bool NVPTXDAGToDAGISel::tryStoreRetval(SDNode *N) {
SDLoc DL(N);
SDValue Chain = N->getOperand(0);
SDValue Offset = N->getOperand(1);
@@ -2840,7 +2862,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreRe
unsigned NumElts = 1;
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case NVPTXISD::StoreRetval:
NumElts = 1;
break;
@@ -2865,11 +2887,11 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreRe
unsigned Opcode = 0;
switch (NumElts) {
default:
- return nullptr;
+ return false;
case 1:
switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i1:
Opcode = NVPTX::StoreRetvalI8;
break;
@@ -2896,7 +2918,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreRe
case 2:
switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i1:
Opcode = NVPTX::StoreRetvalV2I8;
break;
@@ -2923,7 +2945,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreRe
case 4:
switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i1:
Opcode = NVPTX::StoreRetvalV4I8;
break;
@@ -2949,10 +2971,11 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreRe
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return Ret;
+ ReplaceNode(N, Ret);
+ return true;
}
-SDNode *NVPTXDAGToDAGISel::SelectStoreParam(SDNode *N) {
+bool NVPTXDAGToDAGISel::tryStoreParam(SDNode *N) {
SDLoc DL(N);
SDValue Chain = N->getOperand(0);
SDValue Param = N->getOperand(1);
@@ -2966,7 +2989,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStorePa
unsigned NumElts = 1;
switch (N->getOpcode()) {
default:
- return nullptr;
+ return false;
case NVPTXISD::StoreParamU32:
case NVPTXISD::StoreParamS32:
case NVPTXISD::StoreParam:
@@ -2997,11 +3020,11 @@ SDNode *NVPTXDAGToDAGISel::SelectStorePa
default:
switch (NumElts) {
default:
- return nullptr;
+ return false;
case 1:
switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i1:
Opcode = NVPTX::StoreParamI8;
break;
@@ -3028,7 +3051,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStorePa
case 2:
switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i1:
Opcode = NVPTX::StoreParamV2I8;
break;
@@ -3055,7 +3078,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStorePa
case 4:
switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
default:
- return nullptr;
+ return false;
case MVT::i1:
Opcode = NVPTX::StoreParamV4I8;
break;
@@ -3105,17 +3128,17 @@ SDNode *NVPTXDAGToDAGISel::SelectStorePa
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return Ret;
+ ReplaceNode(N, Ret);
+ return true;
}
-SDNode *NVPTXDAGToDAGISel::SelectTextureIntrinsic(SDNode *N) {
+bool NVPTXDAGToDAGISel::tryTextureIntrinsic(SDNode *N) {
SDValue Chain = N->getOperand(0);
- SDNode *Ret = nullptr;
unsigned Opc = 0;
SmallVector<SDValue, 8> Ops;
switch (N->getOpcode()) {
- default: return nullptr;
+ default: return false;
case NVPTXISD::Tex1DFloatS32:
Opc = NVPTX::TEX_1D_F32_S32;
break;
@@ -3628,18 +3651,17 @@ SDNode *NVPTXDAGToDAGISel::SelectTexture
}
Ops.push_back(Chain);
- Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
- return Ret;
+ ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops));
+ return true;
}
-SDNode *NVPTXDAGToDAGISel::SelectSurfaceIntrinsic(SDNode *N) {
+bool NVPTXDAGToDAGISel::trySurfaceIntrinsic(SDNode *N) {
SDValue Chain = N->getOperand(0);
SDValue TexHandle = N->getOperand(1);
- SDNode *Ret = nullptr;
unsigned Opc = 0;
SmallVector<SDValue, 8> Ops;
switch (N->getOpcode()) {
- default: return nullptr;
+ default: return false;
case NVPTXISD::Suld1DI8Clamp:
Opc = NVPTX::SULD_1D_I8_CLAMP;
Ops.push_back(TexHandle);
@@ -4829,14 +4851,14 @@ SDNode *NVPTXDAGToDAGISel::SelectSurface
Ops.push_back(Chain);
break;
}
- Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
- return Ret;
+ ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops));
+ return true;
}
/// SelectBFE - Look for instruction sequences that can be made more efficient
/// by using the 'bfe' (bit-field extract) PTX instruction
-SDNode *NVPTXDAGToDAGISel::SelectBFE(SDNode *N) {
+bool NVPTXDAGToDAGISel::tryBFE(SDNode *N) {
SDLoc DL(N);
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
@@ -4855,7 +4877,7 @@ SDNode *NVPTXDAGToDAGISel::SelectBFE(SDN
ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(RHS);
if (!Mask) {
// We need a constant mask on the RHS of the AND
- return NULL;
+ return false;
}
// Extract the mask bits
@@ -4864,7 +4886,7 @@ SDNode *NVPTXDAGToDAGISel::SelectBFE(SDN
// We *could* handle shifted masks here, but doing so would require an
// 'and' operation to fix up the low-order bits so we would trade
// shr+and for bfe+and, which has the same throughput
- return NULL;
+ return false;
}
// How many bits are in our mask?
@@ -4885,7 +4907,7 @@ SDNode *NVPTXDAGToDAGISel::SelectBFE(SDN
// Do not handle the case where bits have been shifted in. In theory
// we could handle this, but the cost is likely higher than just
// emitting the srl/and pair.
- return NULL;
+ return false;
}
Start = CurDAG->getTargetConstant(StartVal, DL, MVT::i32);
} else {
@@ -4893,20 +4915,20 @@ SDNode *NVPTXDAGToDAGISel::SelectBFE(SDN
// was found) is not constant. We could handle this case, but it would
// require run-time logic that would be more expensive than just
// emitting the srl/and pair.
- return NULL;
+ return false;
}
} else {
// Do not handle the case where the LHS of the and is not a shift. While
// it would be trivial to handle this case, it would just transform
// 'and' -> 'bfe', but 'and' has higher-throughput.
- return NULL;
+ return false;
}
} else if (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) {
if (LHS->getOpcode() == ISD::AND) {
ConstantSDNode *ShiftCnst = dyn_cast<ConstantSDNode>(RHS);
if (!ShiftCnst) {
// Shift amount must be constant
- return NULL;
+ return false;
}
uint64_t ShiftAmt = ShiftCnst->getZExtValue();
@@ -4922,7 +4944,7 @@ SDNode *NVPTXDAGToDAGISel::SelectBFE(SDN
ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(AndRHS);
if (!MaskCnst) {
// Mask must be constant
- return NULL;
+ return false;
}
uint64_t MaskVal = MaskCnst->getZExtValue();
@@ -4942,13 +4964,13 @@ SDNode *NVPTXDAGToDAGISel::SelectBFE(SDN
NumBits = NumZeros + NumOnes - ShiftAmt;
} else {
// This is not a mask we can handle
- return NULL;
+ return false;
}
if (ShiftAmt < NumZeros) {
// Handling this case would require extra logic that would make this
// transformation non-profitable
- return NULL;
+ return false;
}
Val = AndLHS;
@@ -4968,7 +4990,7 @@ SDNode *NVPTXDAGToDAGISel::SelectBFE(SDN
ConstantSDNode *ShlCnst = dyn_cast<ConstantSDNode>(ShlRHS);
if (!ShlCnst) {
// Shift amount must be constant
- return NULL;
+ return false;
}
uint64_t InnerShiftAmt = ShlCnst->getZExtValue();
@@ -4976,20 +4998,20 @@ SDNode *NVPTXDAGToDAGISel::SelectBFE(SDN
ConstantSDNode *ShrCnst = dyn_cast<ConstantSDNode>(ShrRHS);
if (!ShrCnst) {
// Shift amount must be constant
- return NULL;
+ return false;
}
uint64_t OuterShiftAmt = ShrCnst->getZExtValue();
// To avoid extra codegen and be profitable, we need Outer >= Inner
if (OuterShiftAmt < InnerShiftAmt) {
- return NULL;
+ return false;
}
// If the outer shift is more than the type size, we have no bitfield to
// extract (since we also check that the inner shift is <= the outer shift
// then this also implies that the inner shift is < the type size)
if (OuterShiftAmt >= Val.getValueType().getSizeInBits()) {
- return NULL;
+ return false;
}
Start =
@@ -5005,11 +5027,11 @@ SDNode *NVPTXDAGToDAGISel::SelectBFE(SDN
}
} else {
// No can do...
- return NULL;
+ return false;
}
} else {
// No can do...
- return NULL;
+ return false;
}
@@ -5030,14 +5052,15 @@ SDNode *NVPTXDAGToDAGISel::SelectBFE(SDN
}
} else {
// We cannot handle this type
- return NULL;
+ return false;
}
SDValue Ops[] = {
Val, Start, Len
};
- return CurDAG->getMachineNode(Opc, DL, N->getVTList(), Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(Opc, DL, N->getVTList(), Ops));
+ return true;
}
// SelectDirectAddr - Match a direct address for DAG.
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h?rev=269483&r1=269482&r2=269483&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h Fri May 13 16:12:53 2016
@@ -53,22 +53,22 @@ private:
// Include the pieces autogenerated from the target description.
#include "NVPTXGenDAGISel.inc"
- SDNode *SelectImpl(SDNode *N) override;
- SDNode *SelectIntrinsicNoChain(SDNode *N);
- SDNode *SelectIntrinsicChain(SDNode *N);
- SDNode *SelectTexSurfHandle(SDNode *N);
- SDNode *SelectLoad(SDNode *N);
- SDNode *SelectLoadVector(SDNode *N);
- SDNode *SelectLDGLDU(SDNode *N);
- SDNode *SelectStore(SDNode *N);
- SDNode *SelectStoreVector(SDNode *N);
- SDNode *SelectLoadParam(SDNode *N);
- SDNode *SelectStoreRetval(SDNode *N);
- SDNode *SelectStoreParam(SDNode *N);
- SDNode *SelectAddrSpaceCast(SDNode *N);
- SDNode *SelectTextureIntrinsic(SDNode *N);
- SDNode *SelectSurfaceIntrinsic(SDNode *N);
- SDNode *SelectBFE(SDNode *N);
+ void Select(SDNode *N) override;
+ bool tryIntrinsicNoChain(SDNode *N);
+ bool tryIntrinsicChain(SDNode *N);
+ void SelectTexSurfHandle(SDNode *N);
+ bool tryLoad(SDNode *N);
+ bool tryLoadVector(SDNode *N);
+ bool tryLDGLDU(SDNode *N);
+ bool tryStore(SDNode *N);
+ bool tryStoreVector(SDNode *N);
+ bool tryLoadParam(SDNode *N);
+ bool tryStoreRetval(SDNode *N);
+ bool tryStoreParam(SDNode *N);
+ void SelectAddrSpaceCast(SDNode *N);
+ bool tryTextureIntrinsic(SDNode *N);
+ bool trySurfaceIntrinsic(SDNode *N);
+ bool tryBFE(SDNode *N);
inline SDValue getI32Imm(unsigned Imm, SDLoc DL) {
return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
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