[llvm] r269335 - [AArch64] Give function a more appropriate name.

Chad Rosier via llvm-commits llvm-commits at lists.llvm.org
Thu May 12 12:51:58 PDT 2016


Author: mcrosier
Date: Thu May 12 14:51:58 2016
New Revision: 269335

URL: http://llvm.org/viewvc/llvm-project?rev=269335&view=rev
Log:
[AArch64] Give function a more appropriate name.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp?rev=269335&r1=269334&r2=269335&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp Thu May 12 14:51:58 2016
@@ -1984,8 +1984,8 @@ static bool isBitfieldPositioningOp(Sele
 // if yes, given reference arguments will be update so that one can replace
 // the OR instruction with:
 // f = Opc Opd0, Opd1, LSB, MSB ; where Opc is a BFM, LSB = imm, and MSB = imm2
-static SDNode *isBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits,
-                                        SelectionDAG *CurDAG) {
+static SDNode *selectBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits,
+                                            SelectionDAG *CurDAG) {
   assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
 
   SDValue Dst, Src;
@@ -2098,7 +2098,7 @@ SDNode *AArch64DAGToDAGISel::SelectBitfi
     return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,
                                 N->getValueType(0));
 
-  return isBitfieldInsertOpFromOr(N, NUsefulBits, CurDAG);
+  return selectBitfieldInsertOpFromOr(N, NUsefulBits, CurDAG);
 }
 
 /// SelectBitfieldInsertInZeroOp - Match a UBFIZ instruction that is the




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