[llvm] r269258 - SDAG: Implement Select instead of SelectImpl in ARMDAGToDAGISel
Justin Bogner via llvm-commits
llvm-commits at lists.llvm.org
Wed May 11 17:31:09 PDT 2016
Author: bogner
Date: Wed May 11 19:31:09 2016
New Revision: 269258
URL: http://llvm.org/viewvc/llvm-project?rev=269258&view=rev
Log:
SDAG: Implement Select instead of SelectImpl in ARMDAGToDAGISel
This is a large change, but it's pretty mechanical:
- Where we were returning a node before, call ReplaceNode instead.
- Where we would return null to fall back to another selector, rename
the method to try* and return a bool for success.
- Where we were calling SelectNodeTo, just return afterwards.
Part of llvm.org/pr26808.
Modified:
llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=269258&r1=269257&r2=269258&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Wed May 11 19:31:09 2016
@@ -87,7 +87,7 @@ public:
return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
}
- SDNode *SelectImpl(SDNode *N) override;
+ void Select(SDNode *N) override;
bool hasNoVMLxHazardUse(SDNode *N) const;
bool isShifterOpProfitable(const SDValue &Shift,
@@ -198,61 +198,60 @@ public:
#include "ARMGenDAGISel.inc"
private:
- /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
- /// ARM.
- SDNode *SelectARMIndexedLoad(SDNode *N);
- SDNode *SelectT2IndexedLoad(SDNode *N);
+ /// Indexed (pre/post inc/dec) load matching code for ARM.
+ bool tryARMIndexedLoad(SDNode *N);
+ bool tryT2IndexedLoad(SDNode *N);
/// SelectVLD - Select NEON load intrinsics. NumVecs should be
/// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
/// loads of D registers and even subregs and odd subregs of Q registers.
/// For NumVecs <= 2, QOpcodes1 is not used.
- SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
- const uint16_t *DOpcodes,
- const uint16_t *QOpcodes0, const uint16_t *QOpcodes1);
+ void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
+ const uint16_t *DOpcodes, const uint16_t *QOpcodes0,
+ const uint16_t *QOpcodes1);
/// SelectVST - Select NEON store intrinsics. NumVecs should
/// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
/// stores of D registers and even subregs and odd subregs of Q registers.
/// For NumVecs <= 2, QOpcodes1 is not used.
- SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
- const uint16_t *DOpcodes,
- const uint16_t *QOpcodes0, const uint16_t *QOpcodes1);
+ void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
+ const uint16_t *DOpcodes, const uint16_t *QOpcodes0,
+ const uint16_t *QOpcodes1);
/// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
/// be 2, 3 or 4. The opcode arrays specify the instructions used for
/// load/store of D registers and Q registers.
- SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
- bool isUpdating, unsigned NumVecs,
- const uint16_t *DOpcodes, const uint16_t *QOpcodes);
+ void SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating,
+ unsigned NumVecs, const uint16_t *DOpcodes,
+ const uint16_t *QOpcodes);
/// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
/// should be 2, 3 or 4. The opcode array specifies the instructions used
/// for loading D registers. (Q registers are not supported.)
- SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
- const uint16_t *Opcodes);
+ void SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
+ const uint16_t *Opcodes);
/// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
/// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
/// generated to force the table registers to be consecutive.
- SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
+ void SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
- /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
- SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
+ /// Try to select SBFX/UBFX instructions for ARM.
+ bool tryV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
// Select special operations if node forms integer ABS pattern
- SDNode *SelectABSOp(SDNode *N);
+ bool tryABSOp(SDNode *N);
- SDNode *SelectReadRegister(SDNode *N);
- SDNode *SelectWriteRegister(SDNode *N);
+ bool tryReadRegister(SDNode *N);
+ bool tryWriteRegister(SDNode *N);
- SDNode *SelectInlineAsm(SDNode *N);
+ bool tryInlineAsm(SDNode *N);
- SDNode *SelectConcatVector(SDNode *N);
+ void SelectConcatVector(SDNode *N);
- SDNode *SelectSMLAWSMULW(SDNode *N);
+ bool trySMLAWSMULW(SDNode *N);
- SDNode *SelectCMP_SWAP(SDNode *N);
+ void SelectCMP_SWAP(SDNode *N);
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
@@ -1477,11 +1476,11 @@ static inline SDValue getAL(SelectionDAG
return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, dl, MVT::i32);
}
-SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
+bool ARMDAGToDAGISel::tryARMIndexedLoad(SDNode *N) {
LoadSDNode *LD = cast<LoadSDNode>(N);
ISD::MemIndexedMode AM = LD->getAddressingMode();
if (AM == ISD::UNINDEXED)
- return nullptr;
+ return false;
EVT LoadedVT = LD->getMemoryVT();
SDValue Offset, AMOpc;
@@ -1535,26 +1534,28 @@ SDNode *ARMDAGToDAGISel::SelectARMIndexe
SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, AMOpc, getAL(CurDAG, SDLoc(N)),
CurDAG->getRegister(0, MVT::i32), Chain };
- return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
- MVT::i32, MVT::Other, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
+ MVT::i32, MVT::Other, Ops));
+ return true;
} else {
SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG, SDLoc(N)),
CurDAG->getRegister(0, MVT::i32), Chain };
- return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
- MVT::i32, MVT::Other, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
+ MVT::i32, MVT::Other, Ops));
+ return true;
}
}
- return nullptr;
+ return false;
}
-SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
+bool ARMDAGToDAGISel::tryT2IndexedLoad(SDNode *N) {
LoadSDNode *LD = cast<LoadSDNode>(N);
ISD::MemIndexedMode AM = LD->getAddressingMode();
if (AM == ISD::UNINDEXED)
- return nullptr;
+ return false;
EVT LoadedVT = LD->getMemoryVT();
bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
@@ -1581,7 +1582,7 @@ SDNode *ARMDAGToDAGISel::SelectT2Indexed
Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
break;
default:
- return nullptr;
+ return false;
}
Match = true;
}
@@ -1591,11 +1592,12 @@ SDNode *ARMDAGToDAGISel::SelectT2Indexed
SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, Offset, getAL(CurDAG, SDLoc(N)),
CurDAG->getRegister(0, MVT::i32), Chain };
- return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, MVT::i32,
- MVT::Other, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, MVT::i32,
+ MVT::Other, Ops));
+ return true;
}
- return nullptr;
+ return false;
}
/// \brief Form a GPRPair pseudo register from a pair of GPR regs.
@@ -1811,17 +1813,17 @@ static unsigned getVLDSTRegisterUpdateOp
return Opc; // If not one we handle, return it unchanged.
}
-SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
- const uint16_t *DOpcodes,
- const uint16_t *QOpcodes0,
- const uint16_t *QOpcodes1) {
+void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
+ const uint16_t *DOpcodes,
+ const uint16_t *QOpcodes0,
+ const uint16_t *QOpcodes1) {
assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
SDLoc dl(N);
SDValue MemAddr, Align;
unsigned AddrOpIdx = isUpdating ? 1 : 2;
if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
- return nullptr;
+ return;
SDValue Chain = N->getOperand(0);
EVT VT = N->getValueType(0);
@@ -1927,8 +1929,10 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNod
MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
- if (NumVecs == 1)
- return VLd;
+ if (NumVecs == 1) {
+ ReplaceNode(N, VLd);
+ return;
+ }
// Extract out the subregisters.
SDValue SuperReg = SDValue(VLd, 0);
@@ -1942,13 +1946,12 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNod
if (isUpdating)
ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
CurDAG->RemoveDeadNode(N);
- return nullptr;
}
-SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
- const uint16_t *DOpcodes,
- const uint16_t *QOpcodes0,
- const uint16_t *QOpcodes1) {
+void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
+ const uint16_t *DOpcodes,
+ const uint16_t *QOpcodes0,
+ const uint16_t *QOpcodes1) {
assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
SDLoc dl(N);
@@ -1956,7 +1959,7 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNod
unsigned AddrOpIdx = isUpdating ? 1 : 2;
unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
- return nullptr;
+ return;
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
@@ -2048,7 +2051,8 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNod
// Transfer memoperands.
cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
- return VSt;
+ ReplaceNode(N, VSt);
+ return;
}
// Otherwise, quad registers are stored with two separate instructions,
@@ -2089,13 +2093,13 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNod
SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
Ops);
cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
- return VStB;
+ ReplaceNode(N, VStB);
}
-SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
- bool isUpdating, unsigned NumVecs,
- const uint16_t *DOpcodes,
- const uint16_t *QOpcodes) {
+void ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating,
+ unsigned NumVecs,
+ const uint16_t *DOpcodes,
+ const uint16_t *QOpcodes) {
assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
SDLoc dl(N);
@@ -2103,7 +2107,7 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane
unsigned AddrOpIdx = isUpdating ? 1 : 2;
unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
- return nullptr;
+ return;
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
@@ -2194,8 +2198,10 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane
QOpcodes[OpcodeIndex]);
SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
- if (!IsLoad)
- return VLdLn;
+ if (!IsLoad) {
+ ReplaceNode(N, VLdLn);
+ return;
+ }
// Extract the subregisters.
SuperReg = SDValue(VLdLn, 0);
@@ -2209,18 +2215,16 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane
if (isUpdating)
ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
CurDAG->RemoveDeadNode(N);
- return nullptr;
}
-SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
- unsigned NumVecs,
- const uint16_t *Opcodes) {
+void ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
+ const uint16_t *Opcodes) {
assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
SDLoc dl(N);
SDValue MemAddr, Align;
if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
- return nullptr;
+ return;
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
@@ -2293,11 +2297,10 @@ SDNode *ARMDAGToDAGISel::SelectVLDDup(SD
if (isUpdating)
ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
CurDAG->RemoveDeadNode(N);
- return nullptr;
}
-SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
- unsigned Opc) {
+void ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
+ unsigned Opc) {
assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
SDLoc dl(N);
EVT VT = N->getValueType(0);
@@ -2326,13 +2329,12 @@ SDNode *ARMDAGToDAGISel::SelectVTBL(SDNo
Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
Ops.push_back(getAL(CurDAG, dl)); // predicate
Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
- return CurDAG->getMachineNode(Opc, dl, VT, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, Ops));
}
-SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
- bool isSigned) {
+bool ARMDAGToDAGISel::tryV6T2BitfieldExtractOp(SDNode *N, bool isSigned) {
if (!Subtarget->hasV6T2Ops())
- return nullptr;
+ return false;
unsigned Opc = isSigned
? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
@@ -2346,7 +2348,7 @@ SDNode *ARMDAGToDAGISel::SelectV6T2Bitfi
// The immediate is a mask of the low bits iff imm & (imm+1) == 0
if (And_imm & (And_imm + 1))
- return nullptr;
+ return false;
unsigned Srl_imm = 0;
if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
@@ -2366,7 +2368,8 @@ SDNode *ARMDAGToDAGISel::SelectV6T2Bitfi
SDValue Ops[] = { N->getOperand(0).getOperand(0),
CurDAG->getTargetConstant(LSB, dl, MVT::i32),
getAL(CurDAG, dl), Reg0, Reg0 };
- return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
+ return true;
}
// ARM models shift instructions as MOVsi with shifter operand.
@@ -2376,17 +2379,19 @@ SDNode *ARMDAGToDAGISel::SelectV6T2Bitfi
MVT::i32);
SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc,
getAL(CurDAG, dl), Reg0, Reg0 };
- return CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops);
+ return true;
}
SDValue Ops[] = { N->getOperand(0).getOperand(0),
CurDAG->getTargetConstant(LSB, dl, MVT::i32),
CurDAG->getTargetConstant(Width, dl, MVT::i32),
getAL(CurDAG, dl), Reg0 };
- return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
+ return true;
}
}
- return nullptr;
+ return false;
}
// Otherwise, we're looking for a shift of a shift
@@ -2400,13 +2405,14 @@ SDNode *ARMDAGToDAGISel::SelectV6T2Bitfi
unsigned Width = 32 - Srl_imm - 1;
int LSB = Srl_imm - Shl_imm;
if (LSB < 0)
- return nullptr;
+ return false;
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(0).getOperand(0),
CurDAG->getTargetConstant(LSB, dl, MVT::i32),
CurDAG->getTargetConstant(Width, dl, MVT::i32),
getAL(CurDAG, dl), Reg0 };
- return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
+ return true;
}
}
@@ -2415,20 +2421,21 @@ SDNode *ARMDAGToDAGISel::SelectV6T2Bitfi
unsigned LSB = 0;
if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL, LSB) &&
!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRA, LSB))
- return nullptr;
+ return false;
if (LSB + Width > 32)
- return nullptr;
+ return false;
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(0).getOperand(0),
CurDAG->getTargetConstant(LSB, dl, MVT::i32),
CurDAG->getTargetConstant(Width - 1, dl, MVT::i32),
getAL(CurDAG, dl), Reg0 };
- return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
+ return true;
}
- return nullptr;
+ return false;
}
/// Target-specific DAG combining for ISD::XOR.
@@ -2441,16 +2448,16 @@ SDNode *ARMDAGToDAGISel::SelectV6T2Bitfi
/// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
/// ARM instruction selection detects the latter and matches it to
/// ARM::ABS or ARM::t2ABS machine node.
-SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){
+bool ARMDAGToDAGISel::tryABSOp(SDNode *N){
SDValue XORSrc0 = N->getOperand(0);
SDValue XORSrc1 = N->getOperand(1);
EVT VT = N->getValueType(0);
if (Subtarget->isThumb1Only())
- return nullptr;
+ return false;
if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA)
- return nullptr;
+ return false;
SDValue ADDSrc0 = XORSrc0.getOperand(0);
SDValue ADDSrc1 = XORSrc0.getOperand(1);
@@ -2464,10 +2471,11 @@ SDNode *ARMDAGToDAGISel::SelectABSOp(SDN
XType.isInteger() && SRAConstant != nullptr &&
Size == SRAConstant->getZExtValue()) {
unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS;
- return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
+ CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
+ return true;
}
- return nullptr;
+ return false;
}
static bool SearchSignedMulShort(SDValue SignExt, unsigned *Opc, SDValue &Src1,
@@ -2562,7 +2570,7 @@ static bool SearchSignedMulLong(SDValue
return true;
}
-SDNode *ARMDAGToDAGISel::SelectSMLAWSMULW(SDNode *N) {
+bool ARMDAGToDAGISel::trySMLAWSMULW(SDNode *N) {
SDLoc dl(N);
SDValue Src0 = N->getOperand(0);
SDValue Src1 = N->getOperand(1);
@@ -2571,7 +2579,7 @@ SDNode *ARMDAGToDAGISel::SelectSMLAWSMUL
if (N->getOpcode() == ISD::ADD) {
if (Src0.getOpcode() != ISD::OR && Src1.getOpcode() != ISD::OR)
- return nullptr;
+ return false;
SDValue Acc;
if (SearchSignedMulLong(Src0, &Opc, A, B, true)) {
@@ -2579,28 +2587,30 @@ SDNode *ARMDAGToDAGISel::SelectSMLAWSMUL
} else if (SearchSignedMulLong(Src1, &Opc, A, B, true)) {
Acc = Src0;
} else {
- return nullptr;
+ return false;
}
if (Opc == 0)
- return nullptr;
+ return false;
SDValue Ops[] = { A, B, Acc, getAL(CurDAG, dl),
CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->SelectNodeTo(N, Opc, MVT::i32, MVT::Other, Ops);
+ CurDAG->SelectNodeTo(N, Opc, MVT::i32, MVT::Other, Ops);
+ return true;
} else if (N->getOpcode() == ISD::OR &&
SearchSignedMulLong(SDValue(N, 0), &Opc, A, B, false)) {
if (Opc == 0)
- return nullptr;
+ return false;
SDValue Ops[] = { A, B, getAL(CurDAG, dl),
CurDAG->getRegister(0, MVT::i32)};
- return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
+ return true;
}
- return nullptr;
+ return false;
}
/// We've got special pseudo-instructions for these
-SDNode *ARMDAGToDAGISel::SelectCMP_SWAP(SDNode *N) {
+void ARMDAGToDAGISel::SelectCMP_SWAP(SDNode *N) {
unsigned Opcode;
EVT MemTy = cast<MemSDNode>(N)->getMemoryVT();
if (MemTy == MVT::i8)
@@ -2625,61 +2635,50 @@ SDNode *ARMDAGToDAGISel::SelectCMP_SWAP(
ReplaceUses(SDValue(N, 0), SDValue(CmpSwap, 0));
ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 2));
CurDAG->RemoveDeadNode(N);
- return nullptr;
}
-SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
+void ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
// The only time a CONCAT_VECTORS operation can have legal types is when
// two 64-bit vectors are concatenated to a 128-bit vector.
EVT VT = N->getValueType(0);
if (!VT.is128BitVector() || N->getNumOperands() != 2)
llvm_unreachable("unexpected CONCAT_VECTORS");
- return createDRegPairNode(VT, N->getOperand(0), N->getOperand(1));
+ ReplaceNode(N, createDRegPairNode(VT, N->getOperand(0), N->getOperand(1)));
}
-SDNode *ARMDAGToDAGISel::SelectImpl(SDNode *N) {
+void ARMDAGToDAGISel::Select(SDNode *N) {
SDLoc dl(N);
if (N->isMachineOpcode()) {
N->setNodeId(-1);
- return nullptr; // Already selected.
+ return; // Already selected.
}
switch (N->getOpcode()) {
default: break;
case ISD::ADD:
- case ISD::OR: {
- SDNode *ResNode = SelectSMLAWSMULW(N);
- if (ResNode)
- return ResNode;
+ case ISD::OR:
+ if (trySMLAWSMULW(N))
+ return;
break;
- }
- case ISD::WRITE_REGISTER: {
- SDNode *ResNode = SelectWriteRegister(N);
- if (ResNode)
- return ResNode;
+ case ISD::WRITE_REGISTER:
+ if (tryWriteRegister(N))
+ return;
break;
- }
- case ISD::READ_REGISTER: {
- SDNode *ResNode = SelectReadRegister(N);
- if (ResNode)
- return ResNode;
+ case ISD::READ_REGISTER:
+ if (tryReadRegister(N))
+ return;
break;
- }
- case ISD::INLINEASM: {
- SDNode *ResNode = SelectInlineAsm(N);
- if (ResNode)
- return ResNode;
+ case ISD::INLINEASM:
+ if (tryInlineAsm(N))
+ return;
break;
- }
- case ISD::XOR: {
+ case ISD::XOR:
// Select special operations if XOR node forms integer ABS pattern
- SDNode *ResNode = SelectABSOp(N);
- if (ResNode)
- return ResNode;
+ if (tryABSOp(N))
+ return;
// Other cases are autogenerated.
break;
- }
case ISD::Constant: {
unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
// If we can't materialize the constant we need to use a literal pool
@@ -2703,11 +2702,11 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
CurDAG->getRegister(0, MVT::i32),
CurDAG->getEntryNode()
};
- ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
- Ops);
+ ResNode = CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
+ Ops);
}
ReplaceNode(N, ResNode);
- return nullptr;
+ return;
}
// Other cases are autogenerated.
@@ -2724,25 +2723,27 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
MachineFrameInfo *MFI = MF->getFrameInfo();
if (MFI->getObjectAlignment(FI) < 4)
MFI->setObjectAlignment(FI, 4);
- return CurDAG->SelectNodeTo(N, ARM::tADDframe, MVT::i32, TFI,
- CurDAG->getTargetConstant(0, dl, MVT::i32));
+ CurDAG->SelectNodeTo(N, ARM::tADDframe, MVT::i32, TFI,
+ CurDAG->getTargetConstant(0, dl, MVT::i32));
+ return;
} else {
unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
ARM::t2ADDri : ARM::ADDri);
SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, dl, MVT::i32),
getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
+ return;
}
}
case ISD::SRL:
- if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
- return I;
+ if (tryV6T2BitfieldExtractOp(N, false))
+ return;
break;
case ISD::SIGN_EXTEND_INREG:
case ISD::SRA:
- if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
- return I;
+ if (tryV6T2BitfieldExtractOp(N, true))
+ return;
break;
case ISD::MUL:
if (Subtarget->isThumb1Only())
@@ -2760,11 +2761,13 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
if (Subtarget->isThumb()) {
SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
- return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops);
+ return;
} else {
SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
Reg0 };
- return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops);
+ return;
}
}
if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
@@ -2777,19 +2780,21 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
if (Subtarget->isThumb()) {
SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
- return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops);
+ return;
} else {
SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
Reg0 };
- return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops);
+ return;
}
}
}
break;
case ISD::AND: {
// Check for unsigned bitfield extract
- if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
- return I;
+ if (tryV6T2BitfieldExtractOp(N, false))
+ return;
// (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
// of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
@@ -2822,29 +2827,34 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
dl, MVT::i32);
SDValue Ops[] = { N0.getOperand(0), Imm16,
getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->getMachineNode(Opc, dl, VT, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, Ops));
+ return;
}
}
break;
}
case ARMISD::VMOVRRD:
- return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
- N->getOperand(0), getAL(CurDAG, dl),
- CurDAG->getRegister(0, MVT::i32));
+ ReplaceNode(N, CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
+ N->getOperand(0), getAL(CurDAG, dl),
+ CurDAG->getRegister(0, MVT::i32)));
+ return;
case ISD::UMUL_LOHI: {
if (Subtarget->isThumb1Only())
break;
if (Subtarget->isThumb()) {
SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops);
+ ReplaceNode(
+ N, CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops));
+ return;
} else {
SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
- ARM::UMULL : ARM::UMULLv5,
- dl, MVT::i32, MVT::i32, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(
+ Subtarget->hasV6Ops() ? ARM::UMULL : ARM::UMULLv5, dl,
+ MVT::i32, MVT::i32, Ops));
+ return;
}
}
case ISD::SMUL_LOHI: {
@@ -2853,14 +2863,17 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
if (Subtarget->isThumb()) {
SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops);
+ ReplaceNode(
+ N, CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops));
+ return;
} else {
SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
- ARM::SMULL : ARM::SMULLv5,
- dl, MVT::i32, MVT::i32, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(
+ Subtarget->hasV6Ops() ? ARM::SMULL : ARM::SMULLv5, dl,
+ MVT::i32, MVT::i32, Ops));
+ return;
}
}
case ARMISD::UMLAL:{
@@ -2868,15 +2881,18 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
N->getOperand(3), getAL(CurDAG, dl),
CurDAG->getRegister(0, MVT::i32)};
- return CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops);
+ ReplaceNode(
+ N, CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops));
+ return;
}else{
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
N->getOperand(3), getAL(CurDAG, dl),
CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
- ARM::UMLAL : ARM::UMLALv5,
- dl, MVT::i32, MVT::i32, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(
+ Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl,
+ MVT::i32, MVT::i32, Ops));
+ return;
}
}
case ARMISD::SMLAL:{
@@ -2884,25 +2900,26 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
N->getOperand(3), getAL(CurDAG, dl),
CurDAG->getRegister(0, MVT::i32)};
- return CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops);
+ ReplaceNode(
+ N, CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops));
+ return;
}else{
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
N->getOperand(3), getAL(CurDAG, dl),
CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
- ARM::SMLAL : ARM::SMLALv5,
- dl, MVT::i32, MVT::i32, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(
+ Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl,
+ MVT::i32, MVT::i32, Ops));
+ return;
}
}
case ISD::LOAD: {
- SDNode *ResNode = nullptr;
- if (Subtarget->isThumb() && Subtarget->hasThumb2())
- ResNode = SelectT2IndexedLoad(N);
- else
- ResNode = SelectARMIndexedLoad(N);
- if (ResNode)
- return ResNode;
+ if (Subtarget->isThumb() && Subtarget->hasThumb2()) {
+ if (tryT2IndexedLoad(N))
+ return;
+ } else if (tryARMIndexedLoad(N))
+ return;
// Other cases are autogenerated.
break;
}
@@ -2944,13 +2961,13 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ReplaceUses(SDValue(N, 0),
SDValue(Chain.getNode(), Chain.getResNo()));
CurDAG->RemoveDeadNode(N);
- return nullptr;
+ return;
}
case ARMISD::VZIP: {
unsigned Opc = 0;
EVT VT = N->getValueType(0);
switch (VT.getSimpleVT().SimpleTy) {
- default: return nullptr;
+ default: return;
case MVT::v8i8: Opc = ARM::VZIPd8; break;
case MVT::v4i16: Opc = ARM::VZIPd16; break;
case MVT::v2f32:
@@ -2964,13 +2981,14 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
SDValue Pred = getAL(CurDAG, dl);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
- return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops));
+ return;
}
case ARMISD::VUZP: {
unsigned Opc = 0;
EVT VT = N->getValueType(0);
switch (VT.getSimpleVT().SimpleTy) {
- default: return nullptr;
+ default: return;
case MVT::v8i8: Opc = ARM::VUZPd8; break;
case MVT::v4i16: Opc = ARM::VUZPd16; break;
case MVT::v2f32:
@@ -2984,13 +3002,14 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
SDValue Pred = getAL(CurDAG, dl);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
- return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops));
+ return;
}
case ARMISD::VTRN: {
unsigned Opc = 0;
EVT VT = N->getValueType(0);
switch (VT.getSimpleVT().SimpleTy) {
- default: return nullptr;
+ default: return;
case MVT::v8i8: Opc = ARM::VTRNd8; break;
case MVT::v4i16: Opc = ARM::VTRNd16; break;
case MVT::v2f32:
@@ -3003,7 +3022,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
SDValue Pred = getAL(CurDAG, dl);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
- return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops));
+ return;
}
case ARMISD::BUILD_VECTOR: {
EVT VecVT = N->getValueType(0);
@@ -3011,55 +3031,68 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
unsigned NumElts = VecVT.getVectorNumElements();
if (EltVT == MVT::f64) {
assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
- return createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
+ ReplaceNode(
+ N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1)));
+ return;
}
assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
- if (NumElts == 2)
- return createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
+ if (NumElts == 2) {
+ ReplaceNode(
+ N, createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1)));
+ return;
+ }
assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
- return createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1),
- N->getOperand(2), N->getOperand(3));
+ ReplaceNode(N,
+ createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1),
+ N->getOperand(2), N->getOperand(3)));
+ return;
}
case ARMISD::VLD2DUP: {
static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
ARM::VLD2DUPd32 };
- return SelectVLDDup(N, false, 2, Opcodes);
+ SelectVLDDup(N, false, 2, Opcodes);
+ return;
}
case ARMISD::VLD3DUP: {
static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo,
ARM::VLD3DUPd16Pseudo,
ARM::VLD3DUPd32Pseudo };
- return SelectVLDDup(N, false, 3, Opcodes);
+ SelectVLDDup(N, false, 3, Opcodes);
+ return;
}
case ARMISD::VLD4DUP: {
static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo,
ARM::VLD4DUPd16Pseudo,
ARM::VLD4DUPd32Pseudo };
- return SelectVLDDup(N, false, 4, Opcodes);
+ SelectVLDDup(N, false, 4, Opcodes);
+ return;
}
case ARMISD::VLD2DUP_UPD: {
static const uint16_t Opcodes[] = { ARM::VLD2DUPd8wb_fixed,
ARM::VLD2DUPd16wb_fixed,
ARM::VLD2DUPd32wb_fixed };
- return SelectVLDDup(N, true, 2, Opcodes);
+ SelectVLDDup(N, true, 2, Opcodes);
+ return;
}
case ARMISD::VLD3DUP_UPD: {
static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD,
ARM::VLD3DUPd16Pseudo_UPD,
ARM::VLD3DUPd32Pseudo_UPD };
- return SelectVLDDup(N, true, 3, Opcodes);
+ SelectVLDDup(N, true, 3, Opcodes);
+ return;
}
case ARMISD::VLD4DUP_UPD: {
static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD,
ARM::VLD4DUPd16Pseudo_UPD,
ARM::VLD4DUPd32Pseudo_UPD };
- return SelectVLDDup(N, true, 4, Opcodes);
+ SelectVLDDup(N, true, 4, Opcodes);
+ return;
}
case ARMISD::VLD1_UPD: {
@@ -3071,7 +3104,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ARM::VLD1q16wb_fixed,
ARM::VLD1q32wb_fixed,
ARM::VLD1q64wb_fixed };
- return SelectVLD(N, true, 1, DOpcodes, QOpcodes, nullptr);
+ SelectVLD(N, true, 1, DOpcodes, QOpcodes, nullptr);
+ return;
}
case ARMISD::VLD2_UPD: {
@@ -3082,7 +3116,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
static const uint16_t QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
ARM::VLD2q16PseudoWB_fixed,
ARM::VLD2q32PseudoWB_fixed };
- return SelectVLD(N, true, 2, DOpcodes, QOpcodes, nullptr);
+ SelectVLD(N, true, 2, DOpcodes, QOpcodes, nullptr);
+ return;
}
case ARMISD::VLD3_UPD: {
@@ -3096,7 +3131,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
ARM::VLD3q16oddPseudo_UPD,
ARM::VLD3q32oddPseudo_UPD };
- return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
+ SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
+ return;
}
case ARMISD::VLD4_UPD: {
@@ -3110,7 +3146,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
ARM::VLD4q16oddPseudo_UPD,
ARM::VLD4q32oddPseudo_UPD };
- return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
+ SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
+ return;
}
case ARMISD::VLD2LN_UPD: {
@@ -3119,7 +3156,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ARM::VLD2LNd32Pseudo_UPD };
static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
ARM::VLD2LNq32Pseudo_UPD };
- return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
+ SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
+ return;
}
case ARMISD::VLD3LN_UPD: {
@@ -3128,7 +3166,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ARM::VLD3LNd32Pseudo_UPD };
static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
ARM::VLD3LNq32Pseudo_UPD };
- return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
+ SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
+ return;
}
case ARMISD::VLD4LN_UPD: {
@@ -3137,7 +3176,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ARM::VLD4LNd32Pseudo_UPD };
static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
ARM::VLD4LNq32Pseudo_UPD };
- return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
+ SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
+ return;
}
case ARMISD::VST1_UPD: {
@@ -3149,7 +3189,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ARM::VST1q16wb_fixed,
ARM::VST1q32wb_fixed,
ARM::VST1q64wb_fixed };
- return SelectVST(N, true, 1, DOpcodes, QOpcodes, nullptr);
+ SelectVST(N, true, 1, DOpcodes, QOpcodes, nullptr);
+ return;
}
case ARMISD::VST2_UPD: {
@@ -3160,7 +3201,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
static const uint16_t QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
ARM::VST2q16PseudoWB_fixed,
ARM::VST2q32PseudoWB_fixed };
- return SelectVST(N, true, 2, DOpcodes, QOpcodes, nullptr);
+ SelectVST(N, true, 2, DOpcodes, QOpcodes, nullptr);
+ return;
}
case ARMISD::VST3_UPD: {
@@ -3174,7 +3216,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
ARM::VST3q16oddPseudo_UPD,
ARM::VST3q32oddPseudo_UPD };
- return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
+ SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
+ return;
}
case ARMISD::VST4_UPD: {
@@ -3188,7 +3231,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
ARM::VST4q16oddPseudo_UPD,
ARM::VST4q32oddPseudo_UPD };
- return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
+ SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
+ return;
}
case ARMISD::VST2LN_UPD: {
@@ -3197,7 +3241,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ARM::VST2LNd32Pseudo_UPD };
static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
ARM::VST2LNq32Pseudo_UPD };
- return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
+ SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
+ return;
}
case ARMISD::VST3LN_UPD: {
@@ -3206,7 +3251,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ARM::VST3LNd32Pseudo_UPD };
static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
ARM::VST3LNq32Pseudo_UPD };
- return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
+ SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
+ return;
}
case ARMISD::VST4LN_UPD: {
@@ -3215,7 +3261,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ARM::VST4LNd32Pseudo_UPD };
static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
ARM::VST4LNq32Pseudo_UPD };
- return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
+ SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
+ return;
}
case ISD::INTRINSIC_VOID:
@@ -3287,7 +3334,7 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
}
ReplaceUses(SDValue(N, 2), OutChain);
CurDAG->RemoveDeadNode(N);
- return nullptr;
+ return;
}
case Intrinsic::arm_stlexd:
case Intrinsic::arm_strexd: {
@@ -3325,7 +3372,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
- return St;
+ ReplaceNode(N, St);
+ return;
}
case Intrinsic::arm_neon_vld1: {
@@ -3333,7 +3381,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ARM::VLD1d32, ARM::VLD1d64 };
static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
ARM::VLD1q32, ARM::VLD1q64};
- return SelectVLD(N, false, 1, DOpcodes, QOpcodes, nullptr);
+ SelectVLD(N, false, 1, DOpcodes, QOpcodes, nullptr);
+ return;
}
case Intrinsic::arm_neon_vld2: {
@@ -3341,7 +3390,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ARM::VLD2d32, ARM::VLD1q64 };
static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
ARM::VLD2q32Pseudo };
- return SelectVLD(N, false, 2, DOpcodes, QOpcodes, nullptr);
+ SelectVLD(N, false, 2, DOpcodes, QOpcodes, nullptr);
+ return;
}
case Intrinsic::arm_neon_vld3: {
@@ -3355,7 +3405,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo,
ARM::VLD3q16oddPseudo,
ARM::VLD3q32oddPseudo };
- return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
+ SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
+ return;
}
case Intrinsic::arm_neon_vld4: {
@@ -3369,7 +3420,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo,
ARM::VLD4q16oddPseudo,
ARM::VLD4q32oddPseudo };
- return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
+ SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
+ return;
}
case Intrinsic::arm_neon_vld2lane: {
@@ -3378,7 +3430,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ARM::VLD2LNd32Pseudo };
static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo,
ARM::VLD2LNq32Pseudo };
- return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
+ SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
+ return;
}
case Intrinsic::arm_neon_vld3lane: {
@@ -3387,7 +3440,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ARM::VLD3LNd32Pseudo };
static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo,
ARM::VLD3LNq32Pseudo };
- return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
+ SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
+ return;
}
case Intrinsic::arm_neon_vld4lane: {
@@ -3396,7 +3450,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ARM::VLD4LNd32Pseudo };
static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo,
ARM::VLD4LNq32Pseudo };
- return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
+ SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
+ return;
}
case Intrinsic::arm_neon_vst1: {
@@ -3404,7 +3459,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ARM::VST1d32, ARM::VST1d64 };
static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
ARM::VST1q32, ARM::VST1q64 };
- return SelectVST(N, false, 1, DOpcodes, QOpcodes, nullptr);
+ SelectVST(N, false, 1, DOpcodes, QOpcodes, nullptr);
+ return;
}
case Intrinsic::arm_neon_vst2: {
@@ -3412,7 +3468,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ARM::VST2d32, ARM::VST1q64 };
static uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
ARM::VST2q32Pseudo };
- return SelectVST(N, false, 2, DOpcodes, QOpcodes, nullptr);
+ SelectVST(N, false, 2, DOpcodes, QOpcodes, nullptr);
+ return;
}
case Intrinsic::arm_neon_vst3: {
@@ -3426,7 +3483,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo,
ARM::VST3q16oddPseudo,
ARM::VST3q32oddPseudo };
- return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
+ SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
+ return;
}
case Intrinsic::arm_neon_vst4: {
@@ -3440,7 +3498,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo,
ARM::VST4q16oddPseudo,
ARM::VST4q32oddPseudo };
- return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
+ SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
+ return;
}
case Intrinsic::arm_neon_vst2lane: {
@@ -3449,7 +3508,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ARM::VST2LNd32Pseudo };
static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo,
ARM::VST2LNq32Pseudo };
- return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
+ SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
+ return;
}
case Intrinsic::arm_neon_vst3lane: {
@@ -3458,7 +3518,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ARM::VST3LNd32Pseudo };
static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo,
ARM::VST3LNq32Pseudo };
- return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
+ SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
+ return;
}
case Intrinsic::arm_neon_vst4lane: {
@@ -3467,7 +3528,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
ARM::VST4LNd32Pseudo };
static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo,
ARM::VST4LNq32Pseudo };
- return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
+ SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
+ return;
}
}
break;
@@ -3480,18 +3542,24 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
break;
case Intrinsic::arm_neon_vtbl2:
- return SelectVTBL(N, false, 2, ARM::VTBL2);
+ SelectVTBL(N, false, 2, ARM::VTBL2);
+ return;
case Intrinsic::arm_neon_vtbl3:
- return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
+ SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
+ return;
case Intrinsic::arm_neon_vtbl4:
- return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
+ SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
+ return;
case Intrinsic::arm_neon_vtbx2:
- return SelectVTBL(N, true, 2, ARM::VTBX2);
+ SelectVTBL(N, true, 2, ARM::VTBX2);
+ return;
case Intrinsic::arm_neon_vtbx3:
- return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
+ SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
+ return;
case Intrinsic::arm_neon_vtbx4:
- return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
+ SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
+ return;
}
break;
}
@@ -3505,7 +3573,8 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
Ops.push_back(N->getOperand(1));
Ops.push_back(getAL(CurDAG, dl)); // Predicate
Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
- return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops));
+ return;
}
case ARMISD::VTBL2: {
SDLoc dl(N);
@@ -3521,17 +3590,20 @@ SDNode *ARMDAGToDAGISel::SelectImpl(SDNo
Ops.push_back(N->getOperand(2));
Ops.push_back(getAL(CurDAG, dl)); // Predicate
Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
- return CurDAG->getMachineNode(ARM::VTBL2, dl, VT, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(ARM::VTBL2, dl, VT, Ops));
+ return;
}
case ISD::CONCAT_VECTORS:
- return SelectConcatVector(N);
+ SelectConcatVector(N);
+ return;
case ISD::ATOMIC_CMP_SWAP:
- return SelectCMP_SWAP(N);
+ SelectCMP_SWAP(N);
+ return;
}
- return SelectCode(N);
+ SelectCode(N);
}
// Inspect a register string of the form
@@ -3760,7 +3832,7 @@ static int getARClassRegisterMask(String
// Lower the read_register intrinsic to ARM specific DAG nodes
// using the supplied metadata string to select the instruction node to use
// and the registers/masks to construct as operands for the node.
-SDNode *ARMDAGToDAGISel::SelectReadRegister(SDNode *N){
+bool ARMDAGToDAGISel::tryReadRegister(SDNode *N){
const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(N->getOperand(1));
const MDString *RegString = dyn_cast<MDString>(MD->getMD()->getOperand(0));
bool IsThumb2 = Subtarget->isThumb2();
@@ -3789,7 +3861,8 @@ SDNode *ARMDAGToDAGISel::SelectReadRegis
Ops.push_back(getAL(CurDAG, DL));
Ops.push_back(CurDAG->getRegister(0, MVT::i32));
Ops.push_back(N->getOperand(0));
- return CurDAG->getMachineNode(Opcode, DL, ResTypes, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, ResTypes, Ops));
+ return true;
}
std::string SpecialReg = RegString->getString().lower();
@@ -3799,8 +3872,10 @@ SDNode *ARMDAGToDAGISel::SelectReadRegis
Ops = { CurDAG->getTargetConstant(BankedReg, DL, MVT::i32),
getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
N->getOperand(0) };
- return CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSbanked : ARM::MRSbanked,
- DL, MVT::i32, MVT::Other, Ops);
+ ReplaceNode(
+ N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSbanked : ARM::MRSbanked,
+ DL, MVT::i32, MVT::Other, Ops));
+ return true;
}
// The VFP registers are read by creating SelectionDAG nodes with opcodes
@@ -3820,13 +3895,15 @@ SDNode *ARMDAGToDAGISel::SelectReadRegis
// If an opcode was found then we can lower the read to a VFP instruction.
if (Opcode) {
if (!Subtarget->hasVFP2())
- return nullptr;
+ return false;
if (Opcode == ARM::VMRS_MVFR2 && !Subtarget->hasFPARMv8())
- return nullptr;
+ return false;
Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
N->getOperand(0) };
- return CurDAG->getMachineNode(Opcode, DL, MVT::i32, MVT::Other, Ops);
+ ReplaceNode(N,
+ CurDAG->getMachineNode(Opcode, DL, MVT::i32, MVT::Other, Ops));
+ return true;
}
// If the target is M Class then need to validate that the register string
@@ -3841,12 +3918,14 @@ SDNode *ARMDAGToDAGISel::SelectReadRegis
int SYSmValue = getMClassRegisterMask(Reg, Flags, true, Subtarget);
if (SYSmValue == -1)
- return nullptr;
+ return false;
SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32),
getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
N->getOperand(0) };
- return CurDAG->getMachineNode(ARM::t2MRS_M, DL, MVT::i32, MVT::Other, Ops);
+ ReplaceNode(
+ N, CurDAG->getMachineNode(ARM::t2MRS_M, DL, MVT::i32, MVT::Other, Ops));
+ return true;
}
// Here we know the target is not M Class so we need to check if it is one
@@ -3854,24 +3933,27 @@ SDNode *ARMDAGToDAGISel::SelectReadRegis
if (SpecialReg == "apsr" || SpecialReg == "cpsr") {
Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
N->getOperand(0) };
- return CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRS_AR : ARM::MRS, DL,
- MVT::i32, MVT::Other, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRS_AR : ARM::MRS,
+ DL, MVT::i32, MVT::Other, Ops));
+ return true;
}
if (SpecialReg == "spsr") {
Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
N->getOperand(0) };
- return CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSsys_AR : ARM::MRSsys,
- DL, MVT::i32, MVT::Other, Ops);
+ ReplaceNode(
+ N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSsys_AR : ARM::MRSsys, DL,
+ MVT::i32, MVT::Other, Ops));
+ return true;
}
- return nullptr;
+ return false;
}
// Lower the write_register intrinsic to ARM specific DAG nodes
// using the supplied metadata string to select the instruction node to use
// and the registers/masks to use in the nodes
-SDNode *ARMDAGToDAGISel::SelectWriteRegister(SDNode *N){
+bool ARMDAGToDAGISel::tryWriteRegister(SDNode *N){
const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(N->getOperand(1));
const MDString *RegString = dyn_cast<MDString>(MD->getMD()->getOperand(0));
bool IsThumb2 = Subtarget->isThumb2();
@@ -3901,7 +3983,8 @@ SDNode *ARMDAGToDAGISel::SelectWriteRegi
Ops.push_back(CurDAG->getRegister(0, MVT::i32));
Ops.push_back(N->getOperand(0));
- return CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops));
+ return true;
}
std::string SpecialReg = RegString->getString().lower();
@@ -3910,8 +3993,10 @@ SDNode *ARMDAGToDAGISel::SelectWriteRegi
Ops = { CurDAG->getTargetConstant(BankedReg, DL, MVT::i32), N->getOperand(2),
getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
N->getOperand(0) };
- return CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSRbanked : ARM::MSRbanked,
- DL, MVT::Other, Ops);
+ ReplaceNode(
+ N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSRbanked : ARM::MSRbanked,
+ DL, MVT::Other, Ops));
+ return true;
}
// The VFP registers are written to by creating SelectionDAG nodes with
@@ -3927,10 +4012,11 @@ SDNode *ARMDAGToDAGISel::SelectWriteRegi
if (Opcode) {
if (!Subtarget->hasVFP2())
- return nullptr;
+ return false;
Ops = { N->getOperand(2), getAL(CurDAG, DL),
CurDAG->getRegister(0, MVT::i32), N->getOperand(0) };
- return CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops));
+ return true;
}
std::pair<StringRef, StringRef> Fields;
@@ -3948,12 +4034,13 @@ SDNode *ARMDAGToDAGISel::SelectWriteRegi
}
int SYSmValue = getMClassRegisterMask(Reg, Flags, false, Subtarget);
if (SYSmValue == -1)
- return nullptr;
+ return false;
SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32),
N->getOperand(2), getAL(CurDAG, DL),
CurDAG->getRegister(0, MVT::i32), N->getOperand(0) };
- return CurDAG->getMachineNode(ARM::t2MSR_M, DL, MVT::Other, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(ARM::t2MSR_M, DL, MVT::Other, Ops));
+ return true;
}
// We then check to see if a valid mask can be constructed for one of the
@@ -3964,14 +4051,15 @@ SDNode *ARMDAGToDAGISel::SelectWriteRegi
Ops = { CurDAG->getTargetConstant(Mask, DL, MVT::i32), N->getOperand(2),
getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
N->getOperand(0) };
- return CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSR_AR : ARM::MSR,
- DL, MVT::Other, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSR_AR : ARM::MSR,
+ DL, MVT::Other, Ops));
+ return true;
}
- return nullptr;
+ return false;
}
-SDNode *ARMDAGToDAGISel::SelectInlineAsm(SDNode *N){
+bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
std::vector<SDValue> AsmNodeOperands;
unsigned Flag, Kind;
bool Changed = false;
@@ -4115,12 +4203,13 @@ SDNode *ARMDAGToDAGISel::SelectInlineAsm
if (Glue.getNode())
AsmNodeOperands.push_back(Glue);
if (!Changed)
- return nullptr;
+ return false;
SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
CurDAG->getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
New->setNodeId(-1);
- return New.getNode();
+ ReplaceNode(N, New.getNode());
+ return true;
}
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