[llvm] r268955 - Reapply [X86] Add a new LOW32_ADDR_ACCESS_RBP register class.
Quentin Colombet via llvm-commits
llvm-commits at lists.llvm.org
Tue May 10 10:05:58 PDT 2016
Hi Matthias,
Would you mind taking a look?
The problem is that the register pressure computation disagrees between what is computed for the schedule and what is computed for verification.
By the time I dig into that code, I figured you would have sorted out :).
Thanks,
-Quentin
> On May 10, 2016, at 4:13 AM, Mikael Holmén <mikael.holmen at ericsson.com> wrote:
>
> Hi Quentin,
>
> llc crashes on the attached input when I use your commit:
>
> llc -march=x86-64 -mcpu=corei7 -verify-misched -o /dev/null foo.ll
>
> gives
>
> PDiff: GR8_ABCD_L 1 GR32_TC 1 LOW32_ADDR_ACCESS_with_sub_32bit+GR64_NOREX_and_GR64_TCW64 1 GR64_NOREX_and_GR64_TC 1 LOW32_ADDR_ACCESS_with_sub_32bit+GR64_NOREX_and_GR64_TC 1 GR64_NOREX 1 GR64_TCW64 1 LOW32_ADDR_ACCESS_with_sub_32bit+GR64_TCW64 1 GR64_TC 1 LOW32_ADDR_ACCESS_with_sub_32bit+GR64_TC 1 GR64_TC+GR64_TCW64 1 GR8 1 GR8+GR64_NOREX 1 GR8+GR64_TCW64 1 GR64_NOREX+GR64_TC 1 GR8+GR64_TC 1
> DELTA: %vreg102<def,tied1> = SHR64rCL %vreg102<tied0>, %EFLAGS<imp-def,dead>, %CL<imp-use>; GR64_with_sub_8bit:%vreg102
> CurrMx1 GR16 1
> RegP Delta Mismatch
> UNREACHABLE executed at ../lib/CodeGen/RegisterPressure.cpp:1104!
>
> foo.ll is generated with llvm-stress.
>
> Regards,
> Mikael
>
> On 05/09/2016 09:01 PM, Quentin Colombet via llvm-commits wrote:
>> Author: qcolombet
>> Date: Mon May 9 14:01:46 2016
>> New Revision: 268955
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=268955&view=rev
>> Log:
>> Reapply [X86] Add a new LOW32_ADDR_ACCESS_RBP register class.
>>
>> This reapplies commit r268796, with a fix for the setting of the inline asm
>> constraints. I.e., "mark" LOW32_ADDR_ACCESS_RBP as a GR variant, so that the
>> regular processing of the GR operands (setting of the subregisters) happens.
>>
>> Original commit log:
>> [X86] Add a new LOW32_ADDR_ACCESS_RBP register class.
>>
>> ABIs like NaCl uses 32-bit addresses but have 64-bit frame.
>> The new register class reflects those constraints when choosing a
>> register class for a address access.
>>
>> Modified:
>> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
>> llvm/trunk/lib/Target/X86/X86RegisterInfo.td
>> llvm/trunk/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll
>>
>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=268955&r1=268954&r2=268955&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon May 9 14:01:46 2016
>> @@ -30209,6 +30209,7 @@ static bool isGRClass(const TargetRegist
>> case X86::GR64_NOSPRegClassID:
>> case X86::GR64_NOREX_NOSPRegClassID:
>> case X86::LOW32_ADDR_ACCESSRegClassID:
>> + case X86::LOW32_ADDR_ACCESS_RBPRegClassID:
>> return true;
>> default:
>> return false;
>>
>> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=268955&r1=268954&r2=268955&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon May 9 14:01:46 2016
>> @@ -166,7 +166,15 @@ X86RegisterInfo::getPointerRegClass(cons
>> // we can still use 64-bit register as long as we know the high bits
>> // are zeros.
>> // Reflect that in the returned register class.
>> - return Is64Bit ? &X86::LOW32_ADDR_ACCESSRegClass : &X86::GR32RegClass;
>> + if (Is64Bit) {
>> + // When the target also allows 64-bit frame pointer and we do have a
>> + // frame, this is fine to use it for the address accesses as well.
>> + const X86FrameLowering *TFI = getFrameLowering(MF);
>> + return TFI->hasFP(MF) && TFI->Uses64BitFramePtr
>> + ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
>> + : &X86::LOW32_ADDR_ACCESSRegClass;
>> + }
>> + return &X86::GR32RegClass;
>> case 1: // Normal GPRs except the stack pointer (for encoding reasons).
>> if (Subtarget.isTarget64BitLP64())
>> return &X86::GR64_NOSPRegClass;
>>
>> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=268955&r1=268954&r2=268955&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
>> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Mon May 9 14:01:46 2016
>> @@ -427,6 +427,13 @@ def GR64_NOREX_NOSP : RegisterClass<"X86
>> // which we do not have right now.
>> def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 64, (add GR32, RIP)>;
>>
>> +// When RBP is used as a base pointer in a 32-bit addresses environement,
>> +// this is also safe to use the full register to access addresses.
>> +// Since RBP will never be spilled, stick to a 32 alignment to save
>> +// on memory consumption.
>> +def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32,
>> + (add LOW32_ADDR_ACCESS, RBP)>;
>> +
>> // A class to support the 'A' assembler constraint: EAX then EDX.
>> def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
>>
>>
>> Modified: llvm/trunk/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll?rev=268955&r1=268954&r2=268955&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll Mon May 9 14:01:46 2016
>> @@ -1,6 +1,6 @@
>> -; RUN: llc -mtriple=x86_64-pc-linux < %s | FileCheck %s
>> -; RUN: llc -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s
>> -; RUN: llc -mtriple=x86_64-pc-nacl < %s | FileCheck -check-prefix=NACL %s
>> +; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-linux < %s | FileCheck %s
>> +; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s
>> +; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-nacl < %s | FileCheck -check-prefix=NACL %s
>>
>> ; x32 uses %esp, %ebp as stack and frame pointers
>>
>>
>>
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