[llvm] r268955 - Reapply [X86] Add a new LOW32_ADDR_ACCESS_RBP register class.
Mikael Holmén via llvm-commits
llvm-commits at lists.llvm.org
Tue May 10 04:13:17 PDT 2016
Hi Quentin,
llc crashes on the attached input when I use your commit:
llc -march=x86-64 -mcpu=corei7 -verify-misched -o /dev/null foo.ll
gives
PDiff: GR8_ABCD_L 1 GR32_TC 1
LOW32_ADDR_ACCESS_with_sub_32bit+GR64_NOREX_and_GR64_TCW64 1
GR64_NOREX_and_GR64_TC 1
LOW32_ADDR_ACCESS_with_sub_32bit+GR64_NOREX_and_GR64_TC 1 GR64_NOREX
1 GR64_TCW64 1 LOW32_ADDR_ACCESS_with_sub_32bit+GR64_TCW64 1
GR64_TC 1 LOW32_ADDR_ACCESS_with_sub_32bit+GR64_TC 1
GR64_TC+GR64_TCW64 1 GR8 1 GR8+GR64_NOREX 1 GR8+GR64_TCW64 1
GR64_NOREX+GR64_TC 1 GR8+GR64_TC 1
DELTA: %vreg102<def,tied1> = SHR64rCL %vreg102<tied0>,
%EFLAGS<imp-def,dead>, %CL<imp-use>; GR64_with_sub_8bit:%vreg102
CurrMx1 GR16 1
RegP Delta Mismatch
UNREACHABLE executed at ../lib/CodeGen/RegisterPressure.cpp:1104!
foo.ll is generated with llvm-stress.
Regards,
Mikael
On 05/09/2016 09:01 PM, Quentin Colombet via llvm-commits wrote:
> Author: qcolombet
> Date: Mon May 9 14:01:46 2016
> New Revision: 268955
>
> URL: http://llvm.org/viewvc/llvm-project?rev=268955&view=rev
> Log:
> Reapply [X86] Add a new LOW32_ADDR_ACCESS_RBP register class.
>
> This reapplies commit r268796, with a fix for the setting of the inline asm
> constraints. I.e., "mark" LOW32_ADDR_ACCESS_RBP as a GR variant, so that the
> regular processing of the GR operands (setting of the subregisters) happens.
>
> Original commit log:
> [X86] Add a new LOW32_ADDR_ACCESS_RBP register class.
>
> ABIs like NaCl uses 32-bit addresses but have 64-bit frame.
> The new register class reflects those constraints when choosing a
> register class for a address access.
>
> Modified:
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
> llvm/trunk/lib/Target/X86/X86RegisterInfo.td
> llvm/trunk/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=268955&r1=268954&r2=268955&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon May 9 14:01:46 2016
> @@ -30209,6 +30209,7 @@ static bool isGRClass(const TargetRegist
> case X86::GR64_NOSPRegClassID:
> case X86::GR64_NOREX_NOSPRegClassID:
> case X86::LOW32_ADDR_ACCESSRegClassID:
> + case X86::LOW32_ADDR_ACCESS_RBPRegClassID:
> return true;
> default:
> return false;
>
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=268955&r1=268954&r2=268955&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon May 9 14:01:46 2016
> @@ -166,7 +166,15 @@ X86RegisterInfo::getPointerRegClass(cons
> // we can still use 64-bit register as long as we know the high bits
> // are zeros.
> // Reflect that in the returned register class.
> - return Is64Bit ? &X86::LOW32_ADDR_ACCESSRegClass : &X86::GR32RegClass;
> + if (Is64Bit) {
> + // When the target also allows 64-bit frame pointer and we do have a
> + // frame, this is fine to use it for the address accesses as well.
> + const X86FrameLowering *TFI = getFrameLowering(MF);
> + return TFI->hasFP(MF) && TFI->Uses64BitFramePtr
> + ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
> + : &X86::LOW32_ADDR_ACCESSRegClass;
> + }
> + return &X86::GR32RegClass;
> case 1: // Normal GPRs except the stack pointer (for encoding reasons).
> if (Subtarget.isTarget64BitLP64())
> return &X86::GR64_NOSPRegClass;
>
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=268955&r1=268954&r2=268955&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Mon May 9 14:01:46 2016
> @@ -427,6 +427,13 @@ def GR64_NOREX_NOSP : RegisterClass<"X86
> // which we do not have right now.
> def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 64, (add GR32, RIP)>;
>
> +// When RBP is used as a base pointer in a 32-bit addresses environement,
> +// this is also safe to use the full register to access addresses.
> +// Since RBP will never be spilled, stick to a 32 alignment to save
> +// on memory consumption.
> +def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32,
> + (add LOW32_ADDR_ACCESS, RBP)>;
> +
> // A class to support the 'A' assembler constraint: EAX then EDX.
> def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
>
>
> Modified: llvm/trunk/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll?rev=268955&r1=268954&r2=268955&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll Mon May 9 14:01:46 2016
> @@ -1,6 +1,6 @@
> -; RUN: llc -mtriple=x86_64-pc-linux < %s | FileCheck %s
> -; RUN: llc -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s
> -; RUN: llc -mtriple=x86_64-pc-nacl < %s | FileCheck -check-prefix=NACL %s
> +; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-linux < %s | FileCheck %s
> +; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s
> +; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-nacl < %s | FileCheck -check-prefix=NACL %s
>
> ; x32 uses %esp, %ebp as stack and frame pointers
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>
-------------- next part --------------
; ModuleID = '/tmp/autogen.bc'
source_filename = "/tmp/autogen.bc"
define void @autogen_SD1213(i8*, i32*, i64*, i32, i64, i8) {
BB:
%A4 = alloca i64
%A3 = alloca i64
%A2 = alloca i64
%A1 = alloca i1
%A = alloca i64
%L = load i8, i8* %0
store i8 %L, i8* %0
%E = extractelement <1 x i8> zeroinitializer, i32 0
%Shuff = shufflevector <1 x i8> zeroinitializer, <1 x i8> zeroinitializer, <1 x i32> <i32 1>
%I = insertelement <1 x i8> %Shuff, i8 55, i32 0
%B = add i8 55, %5
%Tr = trunc i8 %B to i1
br label %CF275
CF275: ; preds = %BB
%Sl = select i1 true, i8* %0, i8* %0
%Cmp = icmp eq i8 %B, 55
br label %CF251
CF251: ; preds = %CF251, %CF275
%L5 = load i8, i8* %Sl
store i1 true, i1* %A1
%E6 = extractelement <4 x i1> zeroinitializer, i32 0
br i1 %E6, label %CF251, label %CF254
CF254: ; preds = %CF251
%Shuff7 = shufflevector <1 x i8> zeroinitializer, <1 x i8> %Shuff, <1 x i32> <i32 1>
%I8 = insertelement <16 x i32> zeroinitializer, i32 0, i32 3
%B9 = add i8 %B, %L
%ZE = zext <1 x i8> %Shuff7 to <1 x i32>
%Sl10 = select i1 true, i64 144903, i64 -1
%L11 = load i64, i64* %A
store i8 %L, i8* %Sl
%E12 = extractelement <2 x i32> zeroinitializer, i32 1
%Shuff13 = shufflevector <4 x i1> zeroinitializer, <4 x i1> zeroinitializer, <4 x i32> <i32 undef, i32 4, i32 6, i32 0>
%I14 = insertelement <1 x i8> %Shuff7, i8 %L, i32 0
%B15 = xor i8 %L5, 55
%Tr16 = trunc i64 %Sl10 to i16
%Sl17 = select i1 true, i64 -1, i64 -1
%Cmp18 = icmp sgt <4 x i1> %Shuff13, %Shuff13
%L19 = load i8, i8* %Sl
store i8 55, i8* %Sl
%E20 = extractelement <4 x i1> zeroinitializer, i32 1
br label %CF242
CF242: ; preds = %CF242, %CF254
%Shuff21 = shufflevector <16 x i32> zeroinitializer, <16 x i32> %I8, <16 x i32> <i32 8, i32 10, i32 12, i32 14, i32 16, i32 undef, i32 20, i32 undef, i32 undef, i32 undef, i32 28, i32 30, i32 undef, i32 undef, i32 4, i32 6>
%I22 = insertelement <1 x i8> %Shuff, i8 %E, i32 0
%Tr23 = trunc i16 -1 to i8
%Sl24 = select i1 true, i8 %L5, i8 55
%Cmp25 = icmp sge <16 x i8> zeroinitializer, zeroinitializer
%L26 = load i8, i8* %Sl
store i8 %L5, i8* %Sl
%E27 = extractelement <16 x i32> zeroinitializer, i32 10
%Shuff28 = shufflevector <16 x i32> zeroinitializer, <16 x i32> %I8, <16 x i32> <i32 29, i32 31, i32 undef, i32 3, i32 5, i32 7, i32 9, i32 undef, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27>
%I29 = insertelement <4 x i1> zeroinitializer, i1 true, i32 3
%ZE30 = zext i16 -1 to i64
%Sl31 = select i1 %E20, <16 x i32> %Shuff21, <16 x i32> %I8
%Cmp32 = icmp ne i1 %Tr, %E20
br i1 %Cmp32, label %CF242, label %CF246
CF246: ; preds = %CF246, %CF242
%L33 = load i8, i8* %0
store i8 %L33, i8* %Sl
%E34 = extractelement <4 x i1> %Cmp18, i32 1
br i1 %E34, label %CF246, label %CF250
CF250: ; preds = %CF250, %CF263, %CF246
%Shuff35 = shufflevector <1 x i8> %Shuff7, <1 x i8> %Shuff, <1 x i32> undef
%I36 = insertelement <1 x i8> %Shuff35, i8 -1, i32 0
%Tr37 = trunc i64 %ZE30 to i16
%Sl38 = select i1 true, i1 %Tr, i1 %E20
br i1 %Sl38, label %CF250, label %CF263
CF263: ; preds = %CF250
%Cmp39 = icmp ule i1 true, %E6
br i1 %Cmp39, label %CF250, label %CF259
CF259: ; preds = %CF263
%L40 = load i8, i8* %0
store i8 %B15, i8* %Sl
%E41 = extractelement <4 x i1> %Cmp18, i32 0
br label %CF
CF: ; preds = %CF, %CF272, %CF259
%Shuff42 = shufflevector <4 x i64> zeroinitializer, <4 x i64> zeroinitializer, <4 x i32> <i32 undef, i32 5, i32 7, i32 1>
%I43 = insertelement <16 x i32> %Sl31, i32 %3, i32 5
%Tr44 = trunc i8 %L5 to i1
br i1 %Tr44, label %CF, label %CF239
CF239: ; preds = %CF239, %CF265, %CF262, %CF
%Sl45 = select i1 true, <1 x i8> %I36, <1 x i8> %Shuff7
%Cmp46 = fcmp ule double 0xA115BB0B00F772E, 0x75E1CB8023DFEEFE
br i1 %Cmp46, label %CF239, label %CF265
CF265: ; preds = %CF239
%L47 = load i8, i8* %0
store i8 %L47, i8* %Sl
%E48 = extractelement <1 x i8> %Shuff35, i32 0
%Shuff49 = shufflevector <2 x i8> zeroinitializer, <2 x i8> zeroinitializer, <2 x i32> <i32 undef, i32 3>
%I50 = insertelement <4 x i1> zeroinitializer, i1 %Cmp32, i32 3
%FC = sitofp i16 %Tr37 to float
%Sl51 = select i1 true, <4 x i1> %I50, <4 x i1> zeroinitializer
%Cmp52 = icmp slt i16 %Tr37, %Tr16
br i1 %Cmp52, label %CF239, label %CF252
CF252: ; preds = %CF252, %CF265
%L53 = load i8, i8* %Sl
store i8 %L53, i8* %Sl
%E54 = extractelement <16 x i32> zeroinitializer, i32 1
%Shuff55 = shufflevector <1 x i8> %Shuff7, <1 x i8> zeroinitializer, <1 x i32> zeroinitializer
%I56 = insertelement <4 x i1> %I29, i1 true, i32 0
%ZE57 = zext <4 x i1> %Shuff13 to <4 x i64>
%Sl58 = select i1 true, i8 -1, i8 %B15
%Cmp59 = icmp ult <2 x i8> %Shuff49, %Shuff49
%L60 = load i8, i8* %0
store i8 %L47, i8* %Sl
%E61 = extractelement <4 x i1> %Sl51, i32 0
br i1 %E61, label %CF252, label %CF258
CF258: ; preds = %CF258, %CF252
%Shuff62 = shufflevector <4 x i1> zeroinitializer, <4 x i1> %I29, <4 x i32> <i32 7, i32 1, i32 3, i32 5>
%I63 = insertelement <16 x i32> zeroinitializer, i32 284295, i32 9
%B64 = sub <16 x i32> %I43, %Shuff21
%Tr65 = trunc i32 327507 to i16
%Sl66 = select i1 %E61, double 0xA115BB0B00F772E, double 0x75E1CB8023DFEEFE
%Cmp67 = icmp sgt <16 x i32> zeroinitializer, %I8
%L68 = load i8, i8* %Sl
store i8 %Tr23, i8* %0
%E69 = extractelement <4 x i1> zeroinitializer, i32 2
br i1 %E69, label %CF258, label %CF262
CF262: ; preds = %CF258
%Shuff70 = shufflevector <1 x i8> %Shuff7, <1 x i8> %Shuff, <1 x i32> undef
%I71 = insertelement <1 x i8> %Shuff7, i8 %L5, i32 0
%Tr72 = trunc <16 x i32> %Sl31 to <16 x i16>
%Sl73 = select i1 %Cmp39, i8 59, i8 %L40
%Cmp74 = icmp ne <1 x i8> %Shuff55, zeroinitializer
%L75 = load i8, i8* %Sl
store i8 55, i8* %0
%E76 = extractelement <1 x i8> %Sl45, i32 0
%Shuff77 = shufflevector <4 x i64> %Shuff42, <4 x i64> %Shuff42, <4 x i32> <i32 undef, i32 1, i32 3, i32 5>
%I78 = insertelement <4 x i1> %Shuff13, i1 %Cmp32, i32 1
%B79 = shl <4 x i32> zeroinitializer, zeroinitializer
%FC80 = uitofp i8 %Sl73 to float
%Sl81 = select i1 %E20, i64 %L11, i64 %4
%Cmp82 = icmp ugt <16 x i32> %Sl31, %I8
%L83 = load i8, i8* %0
store i8 %L40, i8* %0
%E84 = extractelement <16 x i32> zeroinitializer, i32 3
%Shuff85 = shufflevector <2 x i8> %Shuff49, <2 x i8> %Shuff49, <2 x i32> <i32 undef, i32 0>
%I86 = insertelement <4 x i1> %Shuff13, i1 true, i32 0
%B87 = sdiv i16 %Tr37, %Tr16
%ZE88 = zext i1 %Cmp to i64
%Sl89 = select i1 true, <16 x i8> zeroinitializer, <16 x i8> zeroinitializer
%Cmp90 = icmp ne <16 x i1> %Cmp82, %Cmp67
%L91 = load i8, i8* %0
store i8 %L33, i8* %0
%E92 = extractelement <1 x i8> %Shuff, i32 0
%Shuff93 = shufflevector <4 x i1> %I56, <4 x i1> %I50, <4 x i32> <i32 2, i32 4, i32 6, i32 0>
%I94 = insertelement <16 x i16> %Tr72, i16 %Tr65, i32 12
%Tr95 = trunc i64 %Sl81 to i32
%Sl96 = select i1 %E20, i1 true, i1 %E69
br i1 %Sl96, label %CF239, label %CF240
CF240: ; preds = %CF240, %CF268, %CF266, %CF245, %CF262
%L97 = load i8, i8* %0
store i8 %L, i8* %0
%E98 = extractelement <2 x i8> %Shuff85, i32 1
%Shuff99 = shufflevector <1 x i8> %I36, <1 x i8> %Shuff35, <1 x i32> undef
%I100 = insertelement <1 x i8> %I, i8 %E48, i32 0
%B101 = or <4 x i64> zeroinitializer, zeroinitializer
%Sl102 = select i1 %Tr44, i8 %L97, i8 55
%Cmp103 = icmp eq <4 x i32> zeroinitializer, zeroinitializer
%L104 = load i8, i8* %Sl
store i8 %5, i8* %Sl
%E105 = extractelement <16 x i32> %I43, i32 5
%Shuff106 = shufflevector <16 x i32> zeroinitializer, <16 x i32> %Shuff21, <16 x i32> <i32 8, i32 10, i32 undef, i32 undef, i32 16, i32 18, i32 undef, i32 22, i32 undef, i32 26, i32 undef, i32 30, i32 0, i32 undef, i32 undef, i32 undef>
%I107 = insertelement <16 x i32> zeroinitializer, i32 %E84, i32 10
%B108 = xor <16 x i32> %I107, %I43
%FC109 = uitofp <16 x i16> %Tr72 to <16 x float>
%Sl110 = select i1 %Sl96, <1 x i8> zeroinitializer, <1 x i8> %Shuff99
%L111 = load i8, i8* %0
store i8 %L83, i8* %0
%E112 = extractelement <1 x i8> %Shuff70, i32 0
%Shuff113 = shufflevector <4 x i1> zeroinitializer, <4 x i1> %I50, <4 x i32> <i32 undef, i32 4, i32 6, i32 undef>
%I114 = insertelement <4 x i1> %Shuff93, i1 true, i32 0
%B115 = lshr i64 401359, %Sl81
%FC116 = uitofp <1 x i8> %Sl110 to <1 x float>
%Sl117 = select i1 %Sl96, i64* %A4, i64* %2
%Cmp118 = fcmp ule <1 x float> %FC116, %FC116
%L119 = load i64, i64* %Sl117
store i64 401359, i64* %Sl117
%E120 = extractelement <1 x i1> %Cmp74, i32 0
br i1 %E120, label %CF240, label %CF256
CF256: ; preds = %CF256, %CF240
%Shuff121 = shufflevector <1 x i1> %Cmp74, <1 x i1> %Cmp118, <1 x i32> zeroinitializer
%I122 = insertelement <16 x i32> zeroinitializer, i32 %E84, i32 8
%B123 = udiv i32 %3, %E54
%Se = sext <4 x i1> %I56 to <4 x i8>
%Sl124 = select i1 %E61, <4 x i64> %ZE57, <4 x i64> zeroinitializer
%Cmp125 = icmp slt i1 %E34, %Cmp32
br i1 %Cmp125, label %CF256, label %CF268
CF268: ; preds = %CF256
%L126 = load i64, i64* %Sl117
store i64 %Sl81, i64* %Sl117
%E127 = extractelement <1 x i8> %I22, i32 0
%Shuff128 = shufflevector <4 x i1> %I29, <4 x i1> %Shuff13, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%I129 = insertelement <1 x float> %FC116, float %FC, i32 0
%B130 = sub <16 x i32> zeroinitializer, %I8
%Sl131 = select i1 %E120, <4 x i8> %Se, <4 x i8> %Se
%Cmp132 = icmp uge i64 401359, %ZE30
br i1 %Cmp132, label %CF240, label %CF247
CF247: ; preds = %CF247, %CF274, %CF270, %CF268
%L133 = load i64, i64* %Sl117
store i64 401359, i64* %Sl117
%E134 = extractelement <1 x i8> %Shuff70, i32 0
%Shuff135 = shufflevector <16 x i32> %Shuff106, <16 x i32> %Shuff28, <16 x i32> <i32 2, i32 4, i32 6, i32 8, i32 undef, i32 undef, i32 undef, i32 16, i32 18, i32 20, i32 undef, i32 24, i32 26, i32 28, i32 undef, i32 0>
%I136 = insertelement <1 x i8> %I71, i8 %L83, i32 0
%B137 = or i8 %L111, 55
%FC138 = sitofp i64 %L11 to double
%Sl139 = select i1 true, <1 x i8> %Shuff70, <1 x i8> %Sl45
%Cmp140 = icmp uge i1 true, false
br i1 %Cmp140, label %CF247, label %CF260
CF260: ; preds = %CF260, %CF247
%L141 = load i8, i8* %0
store i64 %Sl81, i64* %Sl117
%E142 = extractelement <4 x i1> zeroinitializer, i32 3
br i1 %E142, label %CF260, label %CF274
CF274: ; preds = %CF260
%Shuff143 = shufflevector <1 x i8> %Shuff, <1 x i8> %Shuff35, <1 x i32> zeroinitializer
%I144 = insertelement <4 x i1> %Shuff128, i1 %Cmp32, i32 2
%FC145 = sitofp <4 x i1> zeroinitializer to <4 x double>
%Sl146 = select i1 true, i8 %L111, i8 %L83
%Cmp147 = icmp ugt i1 %Cmp132, %E120
br i1 %Cmp147, label %CF247, label %CF257
CF257: ; preds = %CF257, %CF274
%L148 = load i64, i64* %Sl117
store i64 %L148, i64* %Sl117
%E149 = extractelement <1 x i8> %Sl139, i32 0
%Shuff150 = shufflevector <1 x i8> %Shuff35, <1 x i8> %I14, <1 x i32> undef
%I151 = insertelement <16 x i8> %Sl89, i8 %L40, i32 9
%FC152 = fptoui <1 x float> %I129 to <1 x i16>
%Sl153 = select i1 %Cmp132, <1 x i8> %Shuff, <1 x i8> %I136
%Cmp154 = icmp sge <4 x i64> %Shuff42, %Sl124
%L155 = load i64, i64* %Sl117
store i64 %L148, i64* %Sl117
%E156 = extractelement <4 x i1> %Cmp154, i32 2
br i1 %E156, label %CF257, label %CF270
CF270: ; preds = %CF257
%Shuff157 = shufflevector <2 x i8> %Shuff85, <2 x i8> zeroinitializer, <2 x i32> <i32 1, i32 undef>
%I158 = insertelement <1 x i8> %Shuff55, i8 55, i32 0
%B159 = fsub <1 x float> %I129, %FC116
%PC = bitcast i64* %2 to i1*
%Sl160 = select i1 %Cmp132, i1 %Cmp32, i1 %Cmp140
br i1 %Sl160, label %CF247, label %CF248
CF248: ; preds = %CF248, %CF276, %CF270
%Cmp161 = icmp ne i32 327507, %Tr95
br i1 %Cmp161, label %CF248, label %CF276
CF276: ; preds = %CF248
%L162 = load i1, i1* %PC
br i1 %L162, label %CF248, label %CF266
CF266: ; preds = %CF276
store i64 %L126, i64* %Sl117
%E163 = extractelement <4 x i1> zeroinitializer, i32 3
br i1 %E163, label %CF240, label %CF245
CF245: ; preds = %CF266
%Shuff164 = shufflevector <1 x i1> %Cmp74, <1 x i1> %Cmp74, <1 x i32> zeroinitializer
%I165 = insertelement <1 x i8> %Shuff, i8 %E134, i32 0
%B166 = and i8 %Sl73, %L75
%Se167 = sext <4 x i1> %I114 to <4 x i32>
%Sl168 = select i1 %E120, <1 x i8> %Shuff99, <1 x i8> %Shuff
%Cmp169 = icmp ne i16 %Tr37, %B87
br i1 %Cmp169, label %CF240, label %CF244
CF244: ; preds = %CF244, %CF245
%L170 = load i8, i8* %Sl
store i64 %B115, i64* %Sl117
%E171 = extractelement <1 x i8> %Shuff70, i32 0
%Shuff172 = shufflevector <1 x i8> %Shuff99, <1 x i8> %Sl153, <1 x i32> <i32 1>
%I173 = insertelement <4 x i1> %I50, i1 %Cmp169, i32 3
%B174 = srem <16 x i32> %B108, %Shuff106
%ZE175 = zext <16 x i16> %Tr72 to <16 x i32>
%Sl176 = select i1 false, i64* %A, i64* %2
%Cmp177 = icmp sgt <16 x i1> %Cmp25, %Cmp25
%L178 = load i64, i64* %Sl117
store i8 %L40, i8* %Sl
%E179 = extractelement <2 x i32> zeroinitializer, i32 0
%Shuff180 = shufflevector <1 x i1> %Shuff164, <1 x i1> %Shuff164, <1 x i32> <i32 1>
%I181 = insertelement <1 x i8> %Shuff55, i8 %L111, i32 0
%B182 = urem i32 %E84, %E179
%Se183 = sext i1 %E6 to i32
%Sl184 = select i1 %Cmp140, i32 %E105, i32 %E179
%Cmp185 = icmp sge <16 x i1> %Cmp67, %Cmp82
%L186 = load i64, i64* %Sl117
store i1 %E20, i1* %PC
%E187 = extractelement <16 x i32> %Shuff135, i32 9
%Shuff188 = shufflevector <1 x i8> %I100, <1 x i8> %I136, <1 x i32> zeroinitializer
%I189 = insertelement <4 x i64> %Shuff42, i64 -1, i32 0
%Sl190 = select i1 %E120, <1 x i8> %I158, <1 x i8> zeroinitializer
%Cmp191 = icmp slt <1 x i8> %I181, %Sl139
%L192 = load i1, i1* %PC
br i1 %L192, label %CF244, label %CF272
CF272: ; preds = %CF244
store i64 %L148, i64* %Sl117
%E193 = extractelement <16 x i32> %Shuff135, i32 0
%Shuff194 = shufflevector <1 x i8> %Shuff188, <1 x i8> %I136, <1 x i32> <i32 1>
%I195 = insertelement <16 x i32> zeroinitializer, i32 %E179, i32 7
%PC196 = bitcast i64* %A to i32*
%Sl197 = select i1 %E156, i32 %E54, i32 %E179
%Cmp198 = icmp sgt i32 %E179, %Tr95
br i1 %Cmp198, label %CF, label %CF238
CF238: ; preds = %CF238, %CF269, %CF267, %CF255, %CF243, %CF272
%L199 = load i8, i8* %Sl
store i64 %B115, i64* %A
%E200 = extractelement <16 x i32> zeroinitializer, i32 6
%Shuff201 = shufflevector <4 x i1> %Cmp154, <4 x i1> %Cmp103, <4 x i32> <i32 1, i32 3, i32 5, i32 undef>
%I202 = insertelement <4 x i1> %Shuff201, i1 %E120, i32 3
%B203 = and <4 x i64> %Shuff77, %I189
%FC204 = sitofp <1 x i1> %Shuff121 to <1 x double>
%Sl205 = select i1 true, i8 %Sl146, i8 %L
%Cmp206 = icmp uge i1 %E163, %Cmp125
br i1 %Cmp206, label %CF238, label %CF269
CF269: ; preds = %CF238
%L207 = load i1, i1* %PC
br i1 %L207, label %CF238, label %CF267
CF267: ; preds = %CF269
store i8 %L91, i8* %Sl
%E208 = extractelement <4 x i1> %I50, i32 0
br i1 %E208, label %CF238, label %CF249
CF249: ; preds = %CF249, %CF261, %CF267
%Shuff209 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %B79, <4 x i32> <i32 3, i32 5, i32 7, i32 1>
%I210 = insertelement <1 x i8> %Shuff70, i8 %L33, i32 0
%B211 = mul <1 x i8> %I210, %I165
%Se212 = sext i1 %Cmp169 to i8
%Sl213 = select i1 %L192, <16 x i16> %I94, <16 x i16> %Tr72
%Cmp214 = icmp sge i64 -1, %Sl81
br i1 %Cmp214, label %CF249, label %CF261
CF261: ; preds = %CF249
%L215 = load i64, i64* %Sl117
store i8 %L33, i8* %Sl
%E216 = extractelement <1 x i1> %Shuff164, i32 0
br i1 %E216, label %CF249, label %CF255
CF255: ; preds = %CF261
%Shuff217 = shufflevector <16 x i1> %Cmp185, <16 x i1> %Cmp67, <16 x i32> <i32 11, i32 undef, i32 15, i32 undef, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 undef, i32 1, i32 3, i32 5, i32 7, i32 undef>
%I218 = insertelement <16 x i32> %Shuff28, i32 %E179, i32 13
%B219 = udiv i64 24795, %ZE88
%PC220 = bitcast i32* %1 to i32*
%Sl221 = select i1 %E120, i1 %E41, i1 %Cmp125
br i1 %Sl221, label %CF238, label %CF243
CF243: ; preds = %CF255
%Cmp222 = icmp eq i64 144903, 24795
br i1 %Cmp222, label %CF238, label %CF241
CF241: ; preds = %CF241, %CF264, %CF243
%L223 = load i32, i32* %PC220
store i32 %E84, i32* %PC196
%E224 = extractelement <4 x i1> %Shuff201, i32 1
br i1 %E224, label %CF241, label %CF264
CF264: ; preds = %CF241
%Shuff225 = shufflevector <16 x i8> %Sl89, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 2, i32 4, i32 undef, i32 undef, i32 10, i32 undef, i32 14, i32 16, i32 undef, i32 20, i32 undef, i32 24, i32 26, i32 28, i32 30>
%I226 = insertelement <16 x i8> %I151, i8 %L97, i32 2
%B227 = or <1 x i8> %I210, %Shuff143
%FC228 = fptoui <1 x float> %FC116 to <1 x i16>
%Sl229 = select i1 true, <4 x i1> %I56, <4 x i1> %I29
%Cmp230 = icmp slt i64 %L215, %Sl81
br i1 %Cmp230, label %CF241, label %CF253
CF253: ; preds = %CF253, %CF264
%L231 = load i8, i8* %0
store i1 %E34, i1* %PC
%E232 = extractelement <1 x i1> %Shuff164, i32 0
br i1 %E232, label %CF253, label %CF271
CF271: ; preds = %CF271, %CF253
%Shuff233 = shufflevector <16 x i32> zeroinitializer, <16 x i32> %Shuff28, <16 x i32> <i32 27, i32 29, i32 undef, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 undef, i32 21, i32 23, i32 25>
%I234 = insertelement <16 x i1> %Cmp67, i1 %E61, i32 13
%ZE235 = zext i8 %L83 to i16
%Sl236 = select i1 %Cmp32, i8 %L47, i8 %L83
%Cmp237 = fcmp ord double 0xA115BB0B00F772E, 0x75E1CB8023DFEEFE
br i1 %Cmp237, label %CF271, label %CF273
CF273: ; preds = %CF271
store i8 %L53, i8* %Sl
store i1 %L192, i1* %PC
store i32 %E179, i32* %PC220
store i32 %E84, i32* %PC220
store i64 %L119, i64* %Sl117
ret void
}
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