[llvm] r268963 - [X86] Drop the 64-bit alignment for LOW32_ADDR_ACCESS register class.

[Quentin Colombet via llvm-commits]

Author: qcolombet
Date: Mon May  9 14:50:30 2016
New Revision: 268963

URL: http://llvm.org/viewvc/llvm-project?rev=268963&view=rev
Log:
[X86] Drop the 64-bit alignment for LOW32_ADDR_ACCESS register class.

The only 64-bit register in that register class is RIP and it will not
get spilled in the current ABIs.

Modified:
    llvm/trunk/lib/Target/X86/X86RegisterInfo.td

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=268963&r1=268962&r2=268963&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Mon May  9 14:50:30 2016
@@ -421,11 +421,12 @@ def GR64_NOREX_NOSP : RegisterClass<"X86
 // In such cases, it is fine to use RIP as we are sure the 32 high
 // bits are not set. We do not need variants for NOSP as RIP is not
 // allowed there.
-// Alignment is 64 because we have RIP.
+// RIP is not spilled anywhere for now, so stick to 32-bit alignment
+// to save on memory space.
 // FIXME: We could allow all 64bit registers, but we would need
 // something to check that the 32 high bits are not set,
 // which we do not have right now.
-def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 64, (add GR32, RIP)>;
+def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>;
 
 // When RBP is used as a base pointer in a 32-bit addresses environement,
 // this is also safe to use the full register to access addresses.