[llvm] r268896 - [mips][microMIPS] Implement LWP and SWP instructions
Benjamin Kramer via llvm-commits
llvm-commits at lists.llvm.org
Mon May 9 04:12:06 PDT 2016
On Mon, May 9, 2016 at 10:07 AM, Zlatko Buljan via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: zbuljan
> Date: Mon May 9 03:07:28 2016
> New Revision: 268896
>
> URL: http://llvm.org/viewvc/llvm-project?rev=268896&view=rev
> Log:
> [mips][microMIPS] Implement LWP and SWP instructions
> Differential Revision: http://reviews.llvm.org/D10640
>
> Modified:
> llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
> llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
> llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
> llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
> llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
> llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
> llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt
> llvm/trunk/test/MC/Mips/micromips/invalid.s
> llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
> llvm/trunk/test/MC/Mips/micromips32r6/valid.s
> llvm/trunk/test/MC/Mips/micromips64r6/invalid.s
> llvm/trunk/test/MC/Mips/micromips64r6/valid.s
>
> Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=268896&r1=268895&r2=268896&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Mon May 9 03:07:28 2016
> @@ -1007,9 +1007,19 @@ public:
>
> void addRegPairOperands(MCInst &Inst, unsigned N) const {
> assert(N == 2 && "Invalid number of operands!");
> + assert((RegIdx.Kind & RegKind_GPR) && "Invalid access!");
> unsigned RegNo = getRegPair();
> - Inst.addOperand(MCOperand::createReg(RegNo++));
> - Inst.addOperand(MCOperand::createReg(RegNo));
> + AsmParser.warnIfRegIndexIsAT(RegNo, StartLoc);
> + Inst.addOperand(MCOperand::createReg(
> + RegIdx.RegInfo->getRegClass(
> + AsmParser.getABI().AreGprs64bit()
> + ? Mips::GPR64RegClassID
> + : Mips::GPR32RegClassID).getRegister(RegNo++)));
> + Inst.addOperand(MCOperand::createReg(
> + RegIdx.RegInfo->getRegClass(
> + AsmParser.getABI().AreGprs64bit()
> + ? Mips::GPR64RegClassID
> + : Mips::GPR32RegClassID).getRegister(RegNo)));
> }
>
> void addMovePRegPairOperands(MCInst &Inst, unsigned N) const {
> @@ -1156,7 +1166,9 @@ public:
> assert(Kind == k_Token && "Invalid access!");
> return StringRef(Tok.Data, Tok.Length);
> }
> - bool isRegPair() const { return Kind == k_RegPair; }
> + bool isRegPair() const {
> + return Kind == k_RegPair && RegIdx.Index <= 30;
> + }
>
> unsigned getReg() const override {
> // As a special case until we sort out the definition of div/divu, pretend
> @@ -1311,9 +1323,9 @@ public:
> }
>
> static std::unique_ptr<MipsOperand>
> - CreateRegPair(unsigned RegNo, SMLoc S, SMLoc E, MipsAsmParser &Parser) {
> + CreateRegPair(MipsOperand MOP, SMLoc S, SMLoc E, MipsAsmParser &Parser) {
> auto Op = make_unique<MipsOperand>(k_RegPair, Parser);
> - Op->RegIdx.Index = RegNo;
> + Op->RegIdx.Index = MOP.RegIdx.Index;
> Op->StartLoc = S;
> Op->EndLoc = E;
> return Op;
> @@ -3618,11 +3630,15 @@ unsigned MipsAsmParser::checkTargetMatch
> // As described by the Mips32r2 spec, the registers Rd and Rs for
> // jalr.hb must be different.
> // It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction
> + // and registers Rd and Base for microMIPS lwp instruction
> unsigned Opcode = Inst.getOpcode();
>
> if ((Opcode == Mips::JALR_HB || Opcode == Mips::JALRC_HB_MMR6) &&
> (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()))
> return Match_RequiresDifferentSrcAndDst;
> + else if ((Opcode == Mips::LWP_MM || Opcode == Mips::LWP_MMR6) &&
> + (Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()))
> + return Match_RequiresDifferentSrcAndDst;
>
> return Match_Success;
> }
> @@ -3786,6 +3802,9 @@ bool MipsAsmParser::MatchAndEmitInstruct
> case Match_MemSImm11:
> return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
> "expected memory with 11-bit signed offset");
> + case Match_MemSImm12:
> + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
> + "expected memory with 12-bit signed offset");
> case Match_MemSImm16:
> return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
> "expected memory with 16-bit signed offset");
> @@ -4673,9 +4692,9 @@ MipsAsmParser::parseRegisterPair(Operand
>
> SMLoc E = Parser.getTok().getLoc();
> MipsOperand &Op = static_cast<MipsOperand &>(*Operands.back());
> - unsigned Reg = Op.getGPR32Reg();
> +
> Operands.pop_back();
> - Operands.push_back(MipsOperand::CreateRegPair(Reg, S, E, *this));
> + Operands.push_back(MipsOperand::CreateRegPair(Op, S, E, *this));
There's a use after free here because Op is still bound to
Operands.back(). I tried to fix in r268901, but it broke tests. Can
you take a look?
> return MatchOperand_Success;
> }
>
>
> Modified: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=268896&r1=268895&r2=268896&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Mon May 9 03:07:28 2016
> @@ -1552,7 +1552,8 @@ static DecodeStatus DecodeMemMMImm12(MCI
> // fallthrough
> default:
> Inst.addOperand(MCOperand::createReg(Reg));
> - if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
> + if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM ||
> + Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6)
> Inst.addOperand(MCOperand::createReg(Reg+1));
>
> Inst.addOperand(MCOperand::createReg(Base));
>
> Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td?rev=268896&r1=268895&r2=268896&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td (original)
> +++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td Mon May 9 03:07:28 2016
> @@ -978,3 +978,18 @@ class POOL32A_DVPEVP_FM_MMR6<string inst
> let Inst{15-6} = funct;
> let Inst{5-0} = 0b111100;
> }
> +
> +class POOL32B_LWP_SWP_FM_MMR6<bits<4> funct> : MipsR6Inst {
> + bits<5> rd;
> + bits<21> addr;
> + bits<5> base = addr{20-16};
> + bits<12> offset = addr{11-0};
> +
> + bits<32> Inst;
> +
> + let Inst{31-26} = 0x8;
> + let Inst{25-21} = rd;
> + let Inst{20-16} = base;
> + let Inst{15-12} = funct;
> + let Inst{11-0} = offset;
> +}
>
> Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=268896&r1=268895&r2=268896&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Mon May 9 03:07:28 2016
> @@ -75,6 +75,7 @@ class JIC_MMR6_ENC : JMP_IDX_COMPACT_F
> class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
> class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
> class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
> +class LWP_MMR6_ENC : POOL32B_LWP_SWP_FM_MMR6<0x1>;
> class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>;
> class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>;
> class MFC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfc0", 0b00011, 0b111100>;
> @@ -113,6 +114,7 @@ class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6
> class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>;
> class SWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0xa>;
> class SWSP_MMR6_ENC : LOAD_STORE_SP_FM_MM16<0x32>;
> +class SWP_MMR6_ENC : POOL32B_LWP_SWP_FM_MMR6<0x9>;
> class PREFE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b010>;
> class CACHEE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b011>;
> class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x3c5>;
> @@ -526,6 +528,32 @@ class PCREL_MMR6_DESC_BASE<string instr_
> class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
> class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
>
> +class LWP_MMR6_DESC : MMR6Arch<"lwp"> {
> + dag OutOperandList = (outs regpair:$rd);
> + dag InOperandList = (ins mem_simm12:$addr);
> + string AsmString = !strconcat("lwp", "\t$rd, $addr");
> + list<dag> Pattern = [];
> + InstrItinClass Itin = NoItinerary;
> + ComplexPattern Addr = addr;
> + Format f = FrmI;
> + string BaseOpcode = "lwp";
> + string DecoderMethod = "DecodeMemMMImm12";
> + bit mayLoad = 1;
> +}
> +
> +class SWP_MMR6_DESC : MMR6Arch<"swp"> {
> + dag OutOperandList = (outs);
> + dag InOperandList = (ins regpair:$rd, mem_simm12:$addr);
> + string AsmString = !strconcat("swp", "\t$rd, $addr");
> + list<dag> Pattern = [];
> + InstrItinClass Itin = NoItinerary;
> + ComplexPattern Addr = addr;
> + Format f = FrmI;
> + string BaseOpcode = "swp";
> + string DecoderMethod = "DecodeMemMMImm12";
> + bit mayStore = 1;
> +}
> +
> class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
> : MMR6Arch<instr_asm> {
> dag OutOperandList = (outs GPROpnd:$rd);
> @@ -1174,6 +1202,7 @@ def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_D
> def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
> ISA_MICROMIPS32R6;
> def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
> +def LWP_MMR6 : StdMMR6Rel, LWP_MMR6_ENC, LWP_MMR6_DESC, ISA_MICROMIPS32R6;
> def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
> def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6;
> def MTC0_MMR6 : StdMMR6Rel, MTC0_MMR6_ENC, MTC0_MMR6_DESC, ISA_MICROMIPS32R6;
> @@ -1221,6 +1250,7 @@ def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DE
> def SW16_MMR6 : StdMMR6Rel, SW16_MMR6_DESC, SW16_MMR6_ENC, ISA_MICROMIPS32R6;
> def SWM16_MMR6 : StdMMR6Rel, SWM16_MMR6_DESC, SWM16_MMR6_ENC, ISA_MICROMIPS32R6;
> def SWSP_MMR6 : StdMMR6Rel, SWSP_MMR6_DESC, SWSP_MMR6_ENC, ISA_MICROMIPS32R6;
> +def SWP_MMR6 : StdMMR6Rel, SWP_MMR6_ENC, SWP_MMR6_DESC, ISA_MICROMIPS32R6;
> def PREFE_MMR6 : StdMMR6Rel, PREFE_MMR6_ENC, PREFE_MMR6_DESC, ISA_MICROMIPS32R6;
> def CACHEE_MMR6 : StdMMR6Rel, CACHEE_MMR6_ENC, CACHEE_MMR6_DESC,
> ISA_MICROMIPS32R6;
>
> Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=268896&r1=268895&r2=268896&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Mon May 9 03:07:28 2016
> @@ -128,6 +128,21 @@ def mem_mm_4sp : Operand<i32> {
> let OperandType = "OPERAND_MEMORY";
> }
>
> +def MipsMemSimm12AsmOperand : AsmOperandClass {
> + let Name = "MemOffsetSimm12";
> + let SuperClasses = [MipsMemAsmOperand];
> + let RenderMethod = "addMemOperands";
> + let ParserMethod = "parseMemOperand";
> + let PredicateMethod = "isMemWithSimmOffset<12>";
> + let DiagnosticType = "MemSImm12";
> +}
> +
> +def mem_simm12 : mem_generic {
> + let MIOperandInfo = (ops ptr_rc, simm12);
> + let EncoderMethod = "getMemEncoding";
> + let ParserMatchClass = MipsMemSimm12AsmOperand;
> +}
> +
> def jmptarget_mm : Operand<OtherVT> {
> let EncoderMethod = "getJumpTargetOpValueMM";
> }
> @@ -217,6 +232,7 @@ MicroMipsInst16<(outs movep_regpair:$dst
> def RegPairAsmOperand : AsmOperandClass {
> let Name = "RegPair";
> let ParserMethod = "parseRegisterPair";
> + let PredicateMethod = "isRegPair";
> }
>
> def regpair : Operand<i32> {
> @@ -229,7 +245,7 @@ def regpair : Operand<i32> {
>
> class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
> ComplexPattern Addr = addr> :
> - InstSE<(outs), (ins regpair:$rt, mem_mm_12:$addr),
> + InstSE<(outs), (ins regpair:$rt, mem_simm12:$addr),
> !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
> let DecoderMethod = "DecodeMemMMImm12";
> let mayStore = 1;
> @@ -237,7 +253,7 @@ class StorePairMM<string opstr, InstrIti
>
> class LoadPairMM<string opstr, InstrItinClass Itin = NoItinerary,
> ComplexPattern Addr = addr> :
> - InstSE<(outs regpair:$rt), (ins mem_mm_12:$addr),
> + InstSE<(outs regpair:$rt), (ins mem_simm12:$addr),
> !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
> let DecoderMethod = "DecodeMemMMImm12";
> let mayLoad = 1;
>
> Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt?rev=268896&r1=268895&r2=268896&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt (original)
> +++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt Mon May 9 03:07:28 2016
> @@ -307,3 +307,5 @@
> 0x00 0x65 0x10 0x90 # CHECK: srav $2, $3, $5
> 0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7
> 0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5
> +0x22 0x04 0x10 0x08 # CHECK: lwp $16, 8($4)
> +0x22 0x04 0x90 0x08 # CHECK: swp $16, 8($4)
>
> Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt?rev=268896&r1=268895&r2=268896&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt (original)
> +++ llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt Mon May 9 03:07:28 2016
> @@ -256,3 +256,5 @@
> 0x58 0xa4 0x18 0x58 # CHECK: dmuh $3, $4, $5
> 0x58 0xa4 0x18 0x98 # CHECK: dmulu $3, $4, $5
> 0x58 0xa4 0x18 0xd8 # CHECK: dmuhu $3, $4, $5
> +0x22 0x04 0x10 0x08 # CHECK: lwp $16, 8($4)
> +0x22 0x04 0x90 0x08 # CHECK: swp $16, 8($4)
>
> Modified: llvm/trunk/test/MC/Mips/micromips/invalid.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips/invalid.s?rev=268896&r1=268895&r2=268896&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/Mips/micromips/invalid.s (original)
> +++ llvm/trunk/test/MC/Mips/micromips/invalid.s Mon May 9 03:07:28 2016
> @@ -83,3 +83,11 @@
> she $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
> she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
> she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
> + lwp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
> + # FIXME: This ought to point at the $34 but memory is treated as one operand.
> + lwp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
> + lwp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
> + lwp $16, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
> + swp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
> + swp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
> + swp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
>
> Modified: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/invalid.s?rev=268896&r1=268895&r2=268896&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s (original)
> +++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s Mon May 9 03:07:28 2016
> @@ -188,3 +188,11 @@
> swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
> swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
> swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
> + lwp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
> + # FIXME: This ought to point at the $34 but memory is treated as one operand.
> + lwp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
> + lwp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
> + lwp $16, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
> + swp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
> + swp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
> + swp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
>
> Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=268896&r1=268895&r2=268896&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
> +++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Mon May 9 03:07:28 2016
> @@ -327,3 +327,5 @@
> sll $3, 7 # CHECK: sll $3, $3, 7 # encoding: [0x00,0x63,0x38,0x00]
> sra $3, 7 # CHECK: sra $3, $3, 7 # encoding: [0x00,0x63,0x38,0x80]
> srl $3, 7 # CHECK: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40]
> + lwp $16, 8($4) # CHECK: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08]
> + swp $16, 8($4) # CHECK: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08]
>
> Modified: llvm/trunk/test/MC/Mips/micromips64r6/invalid.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/invalid.s?rev=268896&r1=268895&r2=268896&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/Mips/micromips64r6/invalid.s (original)
> +++ llvm/trunk/test/MC/Mips/micromips64r6/invalid.s Mon May 9 03:07:28 2016
> @@ -220,3 +220,11 @@
> swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
> swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
> swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
> + lwp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
> + # FIXME: This ought to point at the $34 but memory is treated as one operand.
> + lwp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
> + lwp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
> + lwp $16, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
> + swp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
> + swp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
> + swp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
>
> Modified: llvm/trunk/test/MC/Mips/micromips64r6/valid.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/valid.s?rev=268896&r1=268895&r2=268896&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/Mips/micromips64r6/valid.s (original)
> +++ llvm/trunk/test/MC/Mips/micromips64r6/valid.s Mon May 9 03:07:28 2016
> @@ -259,5 +259,7 @@ a:
> dmuh $3, $4, $5 # CHECK dmuh $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x58]
> dmulu $3, $4, $5 # CHECK dmulu $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x98]
> dmuhu $3, $4, $5 # CHECK dmuhu $3, $4, $5 # encoding: [0x58,0xa4,0x18,0xd8]
> + lwp $16, 8($4) # CHECK: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08]
> + swp $16, 8($4) # CHECK: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08]
>
> 1:
>
>
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