[PATCH] D19198: [X86][AVX] Generalized matching for target shuffle combines

[Simon Pilgrim via llvm-commits]

RKSimon added inline comments.

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:24007
@@ +24006,3 @@
+
+  if (!FloatDomain)
+    return false;
----------------
delena wrote:
> Why float/int is so important? I think that a one cycle penalty for switching domains was on old (SSE) processors.
Intel SB/IV, NW/BW + SK still exhibit it (although according to Agner the number of cases is diminishing with each iteration) and AMD Jaguar / Bulldozer families still have this as well.

http://www.agner.org/optimize/microarchitecture.pdf

In the longer term this may turn into a case where we should move as much of the shuffle combining as possible to the MC pass (as discussed on PR26183) to allow shuffle combines based on target machine scheduler but nobody seems keen to take on that job......

================
Comment at: test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll:25
@@ -24,4 +24,3 @@
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vmovdqa64 {{.*#+}} zmm2 = [0,0,2,2,4,4,6,6]
-; CHECK-NEXT:    vpermt2pd %zmm1, %zmm2, %zmm0
+; CHECK-NEXT:    vmovddup {{.*#+}} zmm0 = zmm0[0,0,2,2,4,4,6,6]
 ; CHECK-NEXT:    retq
----------------
delena wrote:
> What happens when mask is not -1?
I'll add tests to check what is going on.


Repository:
  rL LLVM

http://reviews.llvm.org/D19198