[llvm] r268811 - [SLPVectorizer][X86] Regenerated SEXT/ZEXT cast vectorization tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri May 6 15:22:19 PDT 2016
Author: rksimon
Date: Fri May 6 17:22:18 2016
New Revision: 268811
URL: http://llvm.org/viewvc/llvm-project?rev=268811&view=rev
Log:
[SLPVectorizer][X86] Regenerated SEXT/ZEXT cast vectorization tests
Added 256-bit vector test as well
Modified:
llvm/trunk/test/Transforms/SLPVectorizer/X86/cast.ll
Modified: llvm/trunk/test/Transforms/SLPVectorizer/X86/cast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SLPVectorizer/X86/cast.ll?rev=268811&r1=268810&r2=268811&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SLPVectorizer/X86/cast.ll (original)
+++ llvm/trunk/test/Transforms/SLPVectorizer/X86/cast.ll Fri May 6 17:22:18 2016
@@ -1,19 +1,26 @@
-; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7 -basicaa -slp-vectorizer -dce -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
+; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx -basicaa -slp-vectorizer -dce -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
-target triple = "x86_64-apple-macosx10.9.0"
-; int foo(int * restrict A, char * restrict B) {
+; int test_sext_4i8_to_4i32(int * restrict A, char * restrict B) {
; A[0] = B[0];
; A[1] = B[1];
; A[2] = B[2];
; A[3] = B[3];
; }
-;CHECK-LABEL: @foo(
-;CHECK: load <4 x i8>
-;CHECK: sext
-;CHECK: store <4 x i32>
-define i32 @foo(i32* noalias nocapture %A, i8* noalias nocapture %B) {
+
+define i32 @test_sext_4i8_to_4i32(i32* noalias nocapture %A, i8* noalias nocapture %B) {
+; CHECK-LABEL: @test_sext_4i8_to_4i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* %B to <4 x i8>*
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, <4 x i8>* [[TMP0]], align 1
+; CHECK-NEXT: [[TMP2:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i32>
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32* %A to <4 x i32>*
+; CHECK-NEXT: store <4 x i32> [[TMP2]], <4 x i32>* [[TMP3]], align 4
+; CHECK-NEXT: ret i32 undef
+;
entry:
%0 = load i8, i8* %B, align 1
%conv = sext i8 %0 to i32
@@ -36,3 +43,82 @@ entry:
ret i32 undef
}
+define i32 @test_zext_4i16_to_4i32(i32* noalias nocapture %A, i16* noalias nocapture %B) {
+; CHECK-LABEL: @test_zext_4i16_to_4i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = bitcast i16* %B to <4 x i16>*
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, <4 x i16>* [[TMP0]], align 1
+; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32* %A to <4 x i32>*
+; CHECK-NEXT: store <4 x i32> [[TMP2]], <4 x i32>* [[TMP3]], align 4
+; CHECK-NEXT: ret i32 undef
+;
+entry:
+ %0 = load i16, i16* %B, align 1
+ %conv = zext i16 %0 to i32
+ store i32 %conv, i32* %A, align 4
+ %arrayidx2 = getelementptr inbounds i16, i16* %B, i64 1
+ %1 = load i16, i16* %arrayidx2, align 1
+ %conv3 = zext i16 %1 to i32
+ %arrayidx4 = getelementptr inbounds i32, i32* %A, i64 1
+ store i32 %conv3, i32* %arrayidx4, align 4
+ %arrayidx5 = getelementptr inbounds i16, i16* %B, i64 2
+ %2 = load i16, i16* %arrayidx5, align 1
+ %conv6 = zext i16 %2 to i32
+ %arrayidx7 = getelementptr inbounds i32, i32* %A, i64 2
+ store i32 %conv6, i32* %arrayidx7, align 4
+ %arrayidx8 = getelementptr inbounds i16, i16* %B, i64 3
+ %3 = load i16, i16* %arrayidx8, align 1
+ %conv9 = zext i16 %3 to i32
+ %arrayidx10 = getelementptr inbounds i32, i32* %A, i64 3
+ store i32 %conv9, i32* %arrayidx10, align 4
+ ret i32 undef
+}
+
+define i64 @test_sext_4i16_to_4i64(i64* noalias nocapture %A, i16* noalias nocapture %B) {
+; SSE-LABEL: @test_sext_4i16_to_4i64(
+; SSE-NEXT: entry:
+; SSE-NEXT: [[TMP0:%.*]] = bitcast i16* %B to <2 x i16>*
+; SSE-NEXT: [[TMP1:%.*]] = load <2 x i16>, <2 x i16>* [[TMP0]], align 1
+; SSE-NEXT: [[TMP2:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i64>
+; SSE-NEXT: [[TMP3:%.*]] = bitcast i64* %A to <2 x i64>*
+; SSE-NEXT: store <2 x i64> [[TMP2]], <2 x i64>* [[TMP3]], align 4
+; SSE-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* %B, i64 2
+; SSE-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i64, i64* %A, i64 2
+; SSE-NEXT: [[TMP4:%.*]] = bitcast i16* [[ARRAYIDX5]] to <2 x i16>*
+; SSE-NEXT: [[TMP5:%.*]] = load <2 x i16>, <2 x i16>* [[TMP4]], align 1
+; SSE-NEXT: [[TMP6:%.*]] = sext <2 x i16> [[TMP5]] to <2 x i64>
+; SSE-NEXT: [[TMP7:%.*]] = bitcast i64* [[ARRAYIDX7]] to <2 x i64>*
+; SSE-NEXT: store <2 x i64> [[TMP6]], <2 x i64>* [[TMP7]], align 4
+; SSE-NEXT: ret i64 undef
+;
+; AVX-LABEL: @test_sext_4i16_to_4i64(
+; AVX-NEXT: entry:
+; AVX-NEXT: [[TMP0:%.*]] = bitcast i16* %B to <4 x i16>*
+; AVX-NEXT: [[TMP1:%.*]] = load <4 x i16>, <4 x i16>* [[TMP0]], align 1
+; AVX-NEXT: [[TMP2:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i64>
+; AVX-NEXT: [[TMP3:%.*]] = bitcast i64* %A to <4 x i64>*
+; AVX-NEXT: store <4 x i64> [[TMP2]], <4 x i64>* [[TMP3]], align 4
+; AVX-NEXT: ret i64 undef
+;
+entry:
+ %0 = load i16, i16* %B, align 1
+ %conv = sext i16 %0 to i64
+ store i64 %conv, i64* %A, align 4
+ %arrayidx2 = getelementptr inbounds i16, i16* %B, i64 1
+ %1 = load i16, i16* %arrayidx2, align 1
+ %conv3 = sext i16 %1 to i64
+ %arrayidx4 = getelementptr inbounds i64, i64* %A, i64 1
+ store i64 %conv3, i64* %arrayidx4, align 4
+ %arrayidx5 = getelementptr inbounds i16, i16* %B, i64 2
+ %2 = load i16, i16* %arrayidx5, align 1
+ %conv6 = sext i16 %2 to i64
+ %arrayidx7 = getelementptr inbounds i64, i64* %A, i64 2
+ store i64 %conv6, i64* %arrayidx7, align 4
+ %arrayidx8 = getelementptr inbounds i16, i16* %B, i64 3
+ %3 = load i16, i16* %arrayidx8, align 1
+ %conv9 = sext i16 %3 to i64
+ %arrayidx10 = getelementptr inbounds i64, i64* %A, i64 3
+ store i64 %conv9, i64* %arrayidx10, align 4
+ ret i64 undef
+}
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