[llvm] r268799 - Revert "[X86] Add a new LOW32_ADDR_ACCESS_RBP register class."

Quentin Colombet via llvm-commits llvm-commits at lists.llvm.org
Fri May 6 14:21:51 PDT 2016


Author: qcolombet
Date: Fri May  6 16:21:50 2016
New Revision: 268799

URL: http://llvm.org/viewvc/llvm-project?rev=268799&view=rev
Log:
Revert "[X86] Add a new LOW32_ADDR_ACCESS_RBP register class."

This reverts commit r268796.
I believe it breaks test/CodeGen/X86/asm-mismatched-types.ll with:
Cannot emit physreg copy instruction

Modified:
    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
    llvm/trunk/lib/Target/X86/X86RegisterInfo.td
    llvm/trunk/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=268799&r1=268798&r2=268799&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Fri May  6 16:21:50 2016
@@ -166,15 +166,7 @@ X86RegisterInfo::getPointerRegClass(cons
     // we can still use 64-bit register as long as we know the high bits
     // are zeros.
     // Reflect that in the returned register class.
-    if (Is64Bit) {
-      // When the target also allows 64-bit frame pointer and we do have a
-      // frame, this is fine to use it for the address accesses as well.
-      const X86FrameLowering *TFI = getFrameLowering(MF);
-      return TFI->hasFP(MF) && TFI->Uses64BitFramePtr
-                 ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
-                 : &X86::LOW32_ADDR_ACCESSRegClass;
-    }
-    return &X86::GR32RegClass;
+    return Is64Bit ? &X86::LOW32_ADDR_ACCESSRegClass : &X86::GR32RegClass;
   case 1: // Normal GPRs except the stack pointer (for encoding reasons).
     if (Subtarget.isTarget64BitLP64())
       return &X86::GR64_NOSPRegClass;

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=268799&r1=268798&r2=268799&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Fri May  6 16:21:50 2016
@@ -427,11 +427,6 @@ def GR64_NOREX_NOSP : RegisterClass<"X86
 // which we do not have right now.
 def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 64, (add GR32, RIP)>;
 
-// When RBP is used as a base pointer in a 32-bit addresses environement,
-// this is also safe to use the full register to access addresses. 
-def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 64,
-                                          (add LOW32_ADDR_ACCESS, RBP)>;
-
 // A class to support the 'A' assembler constraint: EAX then EDX.
 def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
 

Modified: llvm/trunk/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll?rev=268799&r1=268798&r2=268799&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll (original)
+++ llvm/trunk/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll Fri May  6 16:21:50 2016
@@ -1,6 +1,6 @@
-; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-linux < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s
-; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-nacl < %s | FileCheck -check-prefix=NACL %s
+; RUN: llc -mtriple=x86_64-pc-linux < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s
+; RUN: llc -mtriple=x86_64-pc-nacl < %s | FileCheck -check-prefix=NACL %s
 
 ; x32 uses %esp, %ebp as stack and frame pointers
 




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