[llvm] r268730 - [mips][fastisel] Conditional moves do not have implicit operands.

[Daniel Sanders via llvm-commits]

Author: dsanders
Date: Fri May  6 07:57:26 2016
New Revision: 268730

URL: http://llvm.org/viewvc/llvm-project?rev=268730&view=rev
Log:
[mips][fastisel] Conditional moves do not have implicit operands.

Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D19862

Modified:
    llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
    llvm/trunk/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll

Modified: llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFastISel.cpp?rev=268730&r1=268729&r2=268730&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsFastISel.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsFastISel.cpp Fri May  6 07:57:26 2016
@@ -692,11 +692,10 @@ bool MipsFastISel::emitCmp(unsigned Resu
     emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
     emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
         Mips::FCC0, RegState::ImplicitDefine);
-    MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg)
-                                 .addReg(RegWithOne)
-                                 .addReg(Mips::FCC0)
-                                 .addReg(RegWithZero, RegState::Implicit);
-    MI->tieOperands(0, 3);
+    emitInst(CondMovOpc, ResultReg)
+        .addReg(RegWithOne)
+        .addReg(Mips::FCC0)
+        .addReg(RegWithZero);
     break;
   }
   }

Modified: llvm/trunk/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll?rev=268730&r1=268729&r2=268730&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll Fri May  6 07:57:26 2016
@@ -1,7 +1,7 @@
 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
-; RUN:     < %s | FileCheck %s
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
-; RUN:     < %s | FileCheck %s
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
 
 @f1 = common global float 0.000000e+00, align 4
 @f2 = common global float 0.000000e+00, align 4