[llvm] r268051 - [Hexagon] Optimize addressing modes for load/store
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 29 08:49:14 PDT 2016
Author: kparzysz
Date: Fri Apr 29 10:49:13 2016
New Revision: 268051
URL: http://llvm.org/viewvc/llvm-project?rev=268051&view=rev
Log:
[Hexagon] Optimize addressing modes for load/store
Patch by Jyotsna Verma.
Added:
llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp
llvm/trunk/test/CodeGen/Hexagon/opt-addr-mode.ll
Modified:
llvm/trunk/lib/Target/Hexagon/CMakeLists.txt
llvm/trunk/lib/Target/Hexagon/Hexagon.td
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h
llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp
llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp
llvm/trunk/lib/Target/Hexagon/RDFLiveness.h
llvm/trunk/test/CodeGen/Hexagon/tls_pic.ll
llvm/trunk/test/CodeGen/Hexagon/tls_static.ll
llvm/trunk/test/CodeGen/Hexagon/zextloadi1.ll
Modified: llvm/trunk/lib/Target/Hexagon/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/CMakeLists.txt?rev=268051&r1=268050&r2=268051&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/Hexagon/CMakeLists.txt Fri Apr 29 10:49:13 2016
@@ -38,6 +38,7 @@ add_llvm_target(HexagonCodeGen
HexagonMachineScheduler.cpp
HexagonMCInstLower.cpp
HexagonNewValueJump.cpp
+ HexagonOptAddrMode.cpp
HexagonOptimizeSZextends.cpp
HexagonPeephole.cpp
HexagonRDF.cpp
Modified: llvm/trunk/lib/Target/Hexagon/Hexagon.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.td?rev=268051&r1=268050&r2=268051&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/Hexagon.td (original)
+++ llvm/trunk/lib/Target/Hexagon/Hexagon.td Fri Apr 29 10:49:13 2016
@@ -47,7 +47,6 @@ def IEEERndNearV5T : Predicate<"HST-
def UseHVXDbl : Predicate<"HST->useHVXDblOps()">,
AssemblerPredicate<"ExtensionHVXDbl">;
def UseHVXSgl : Predicate<"HST->useHVXSglOps()">;
-
def UseHVX : Predicate<"HST->useHVXSglOps() ||HST->useHVXDblOps()">,
AssemblerPredicate<"ExtensionHVX">;
@@ -171,6 +170,15 @@ def getBaseWithImmOffset : InstrMapping
let ValueCols = [["BaseImmOffset"]];
}
+def getAbsoluteForm : InstrMapping {
+ let FilterClass = "AddrModeRel";
+ let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
+ "isFloat"];
+ let ColFields = ["addrMode"];
+ let KeyCol = ["BaseImmOffset"];
+ let ValueCols = [["Absolute"]];
+}
+
def getBaseWithRegOffset : InstrMapping {
let FilterClass = "AddrModeRel";
let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
@@ -179,6 +187,22 @@ def getBaseWithRegOffset : InstrMapping
let ValueCols = [["BaseRegOffset"]];
}
+def xformRegToImmOffset : InstrMapping {
+ let FilterClass = "AddrModeRel";
+ let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
+ let ColFields = ["addrMode"];
+ let KeyCol = ["BaseRegOffset"];
+ let ValueCols = [["BaseImmOffset"]];
+}
+
+def getBaseWithLongOffset : InstrMapping {
+ let FilterClass = "ImmRegShl";
+ let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
+ let ColFields = ["addrMode"];
+ let KeyCol = ["BaseRegOffset"];
+ let ValueCols = [["BaseLongOffset"]];
+}
+
def getRegForm : InstrMapping {
let FilterClass = "ImmRegRel";
let RowFields = ["CextOpcode", "PredSense", "PNewValue"];
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=268051&r1=268050&r2=268051&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Fri Apr 29 10:49:13 2016
@@ -3022,6 +3022,11 @@ bool HexagonInstrInfo::predOpcodeHasNot(
}
+short HexagonInstrInfo::getAbsoluteForm(const MachineInstr *MI) const {
+ return Hexagon::getAbsoluteForm(MI->getOpcode());
+}
+
+
unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
const uint64_t F = MI->getDesc().TSFlags;
return (F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask;
@@ -3161,6 +3166,23 @@ SmallVector<MachineInstr*, 2> HexagonIns
}
+short HexagonInstrInfo::getBaseWithLongOffset(short Opcode) const {
+ if (Opcode < 0)
+ return -1;
+ return Hexagon::getBaseWithLongOffset(Opcode);
+}
+
+
+short HexagonInstrInfo::getBaseWithLongOffset(const MachineInstr *MI) const {
+ return Hexagon::getBaseWithLongOffset(MI->getOpcode());
+}
+
+
+short HexagonInstrInfo::getBaseWithRegOffset(const MachineInstr *MI) const {
+ return Hexagon::getBaseWithRegOffset(MI->getOpcode());
+}
+
+
// Returns Operand Index for the constant extended instruction.
unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
const uint64_t F = MI->getDesc().TSFlags;
@@ -4161,3 +4183,7 @@ bool HexagonInstrInfo::validateBranchCon
return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
}
+
+short HexagonInstrInfo::xformRegToImmOffset(const MachineInstr *MI) const {
+ return Hexagon::xformRegToImmOffset(MI->getOpcode());
+}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h?rev=268051&r1=268050&r2=268051&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h Fri Apr 29 10:49:13 2016
@@ -343,11 +343,15 @@ public:
bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
+ short getAbsoluteForm(const MachineInstr *MI) const;
unsigned getAddrMode(const MachineInstr* MI) const;
unsigned getBaseAndOffset(const MachineInstr *MI, int &Offset,
unsigned &AccessSize) const;
bool getBaseAndOffsetPosition(const MachineInstr *MI, unsigned &BasePos,
unsigned &OffsetPos) const;
+ short getBaseWithLongOffset(short Opcode) const;
+ short getBaseWithLongOffset(const MachineInstr *MI) const;
+ short getBaseWithRegOffset(const MachineInstr *MI) const;
SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
unsigned getCExtOpNum(const MachineInstr *MI) const;
HexagonII::CompoundGroup
@@ -397,6 +401,7 @@ public:
bool reversePredSense(MachineInstr* MI) const;
unsigned reversePrediction(unsigned Opcode) const;
bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
+ short xformRegToImmOffset(const MachineInstr *MI) const;
};
}
Added: llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp?rev=268051&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp (added)
+++ llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp Fri Apr 29 10:49:13 2016
@@ -0,0 +1,694 @@
+//===--- HexagonOptAddrMode.cpp -------------------------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+// This implements a Hexagon-specific pass to optimize addressing mode for
+// load/store instructions.
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "opt-addr-mode"
+
+#include "HexagonTargetMachine.h"
+#include "RDFGraph.h"
+#include "RDFLiveness.h"
+
+#include "llvm/ADT/DenseSet.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineDominanceFrontier.h"
+#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetRegisterInfo.h"
+
+static cl::opt<int> CodeGrowthLimit("hexagon-amode-growth-limit",
+ cl::Hidden, cl::init(0), cl::desc("Code growth limit for address mode "
+ "optimization"));
+
+using namespace llvm;
+using namespace rdf;
+
+namespace llvm {
+ FunctionPass *createHexagonOptAddrMode();
+ void initializeHexagonOptAddrModePass(PassRegistry &);
+}
+
+namespace {
+class HexagonOptAddrMode : public MachineFunctionPass {
+public:
+ static char ID;
+ HexagonOptAddrMode()
+ : MachineFunctionPass(ID), HII(0), MDT(0), DFG(0), LV(0) {
+ PassRegistry &R = *PassRegistry::getPassRegistry();
+ initializeHexagonOptAddrModePass(R);
+ }
+ const char *getPassName() const override {
+ return "Optimize addressing mode of load/store";
+ }
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ MachineFunctionPass::getAnalysisUsage(AU);
+ AU.addRequired<MachineDominatorTree>();
+ AU.addRequired<MachineDominanceFrontier>();
+ AU.setPreservesAll();
+ }
+ bool runOnMachineFunction(MachineFunction &MF) override;
+
+private:
+ typedef DenseSet<MachineInstr *> MISetType;
+ typedef DenseMap<MachineInstr *, bool> InstrEvalMap;
+ const HexagonInstrInfo *HII;
+ MachineDominatorTree *MDT;
+ DataFlowGraph *DFG;
+ DataFlowGraph::DefStackMap DefM;
+ std::map<RegisterRef, std::map<NodeId, NodeId>> RDefMap;
+ Liveness *LV;
+ MISetType Deleted;
+
+ bool processBlock(NodeAddr<BlockNode *> BA);
+ bool xformUseMI(MachineInstr *TfrMI, MachineInstr *UseMI,
+ NodeAddr<UseNode *> UseN, unsigned UseMOnum);
+ bool analyzeUses(unsigned DefR, const NodeList &UNodeList,
+ InstrEvalMap &InstrEvalResult, short &SizeInc);
+ bool hasRepForm(MachineInstr *MI, unsigned TfrDefR);
+ MachineInstr *getReachedDefMI(NodeAddr<StmtNode *> SN, unsigned OffsetReg,
+ bool &HasReachingDef);
+ bool canRemoveAddasl(NodeAddr<StmtNode *> AddAslSN, MachineInstr *MI,
+ const NodeList &UNodeList);
+ void getAllRealUses(NodeAddr<StmtNode *> SN, NodeList &UNodeList);
+ bool allValidCandidates(NodeAddr<StmtNode *> SA, NodeList &UNodeList);
+ short getBaseWithLongOffset(const MachineInstr *MI) const;
+ void updateMap(NodeAddr<InstrNode *> IA);
+ bool constructDefMap(MachineBasicBlock *B);
+ bool changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
+ unsigned ImmOpNum);
+ bool changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, unsigned ImmOpNum);
+ bool changeAddAsl(NodeAddr<UseNode *> AddAslUN, MachineInstr *AddAslMI,
+ const MachineOperand &ImmOp, unsigned ImmOpNum);
+};
+}
+
+char HexagonOptAddrMode::ID = 0;
+
+INITIALIZE_PASS_BEGIN(HexagonOptAddrMode, "opt-amode",
+ "Optimize addressing mode", false, false)
+INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
+INITIALIZE_PASS_DEPENDENCY(MachineDominanceFrontier)
+INITIALIZE_PASS_END(HexagonOptAddrMode, "opt-amode", "Optimize addressing mode",
+ false, false)
+
+bool HexagonOptAddrMode::hasRepForm(MachineInstr *MI, unsigned TfrDefR) {
+ const MCInstrDesc &MID = MI->getDesc();
+
+ if ((!MID.mayStore() && !MID.mayLoad()) || HII->isPredicated(*MI))
+ return false;
+
+ if (MID.mayStore()) {
+ MachineOperand StOp = MI->getOperand(MI->getNumOperands() - 1);
+ if (StOp.isReg() && StOp.getReg() == TfrDefR)
+ return false;
+ }
+
+ if (HII->getAddrMode(MI) == HexagonII::BaseRegOffset)
+ // Tranform to Absolute plus register offset.
+ return (HII->getBaseWithLongOffset(MI) >= 0);
+ else if (HII->getAddrMode(MI) == HexagonII::BaseImmOffset)
+ // Tranform to absolute addressing mode.
+ return (HII->getAbsoluteForm(MI) >= 0);
+
+ return false;
+}
+
+MachineInstr *HexagonOptAddrMode::getReachedDefMI(NodeAddr<StmtNode *> SN,
+ unsigned OffsetReg,
+ bool &HasReachingDef) {
+ MachineInstr *ReachedDefMI = NULL;
+ NodeId RD = 0;
+ for (NodeAddr<UseNode *> UN : SN.Addr->members_if(DFG->IsUse, *DFG)) {
+ RegisterRef UR = UN.Addr->getRegRef();
+ if (OffsetReg == UR.Reg) {
+ RD = UN.Addr->getReachingDef();
+ if (!RD)
+ continue;
+ HasReachingDef = true;
+ }
+ }
+ if (HasReachingDef) {
+ NodeAddr<DefNode *> RDN = DFG->addr<DefNode *>(RD);
+ NodeAddr<StmtNode *> ReachingIA = RDN.Addr->getOwner(*DFG);
+ DEBUG(dbgs() << "\t\t\t[Def Node]: "
+ << Print<NodeAddr<InstrNode *>>(ReachingIA, *DFG) << "\n");
+ NodeId ReachedID = RDN.Addr->getReachedDef();
+ if (!ReachedID)
+ return ReachedDefMI;
+
+ NodeAddr<DefNode *> ReachedDN = DFG->addr<DefNode *>(ReachedID);
+ NodeAddr<StmtNode *> ReachedIA = ReachedDN.Addr->getOwner(*DFG);
+ DEBUG(dbgs() << "\t\t\t[Reached Def Node]: "
+ << Print<NodeAddr<InstrNode *>>(ReachedIA, *DFG) << "\n");
+ ReachedDefMI = ReachedIA.Addr->getCode();
+ DEBUG(dbgs() << "\nReached Def MI === " << *ReachedDefMI << "\n");
+ }
+ return ReachedDefMI;
+}
+
+// Check if addasl instruction can be removed. This is possible only
+// if it's feeding to only load/store instructions with base + register
+// offset as these instruction can be tranformed to use 'absolute plus
+// shifted register offset'.
+// ex:
+// Rs = ##foo
+// Rx = addasl(Rs, Rt, #2)
+// Rd = memw(Rx + #28)
+// Above three instructions can be replaced with Rd = memw(Rt<<#2 + ##foo+28)
+
+bool HexagonOptAddrMode::canRemoveAddasl(NodeAddr<StmtNode *> AddAslSN,
+ MachineInstr *MI,
+ const NodeList &UNodeList) {
+ // check offset size in addasl. if 'offset > 3' return false
+ const MachineOperand &OffsetOp = MI->getOperand(3);
+ if (!OffsetOp.isImm() || OffsetOp.getImm() > 3)
+ return false;
+
+ unsigned OffsetReg = MI->getOperand(2).getReg();
+ RegisterRef OffsetRR;
+ NodeId OffsetRegRD = 0;
+ for (NodeAddr<UseNode *> UA : AddAslSN.Addr->members_if(DFG->IsUse, *DFG)) {
+ RegisterRef RR = UA.Addr->getRegRef();
+ if (OffsetReg == RR.Reg) {
+ OffsetRR = RR;
+ OffsetRegRD = UA.Addr->getReachingDef();
+ }
+ }
+
+ for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
+ NodeAddr<UseNode *> UA = *I;
+ NodeAddr<InstrNode *> IA = UA.Addr->getOwner(*DFG);
+ if ((UA.Addr->getFlags() & NodeAttrs::PhiRef) ||
+ RDefMap[OffsetRR][IA.Id] != OffsetRegRD)
+ return false;
+
+ MachineInstr *UseMI = NodeAddr<StmtNode *>(IA).Addr->getCode();
+ NodeAddr<DefNode *> OffsetRegDN = DFG->addr<DefNode *>(OffsetRegRD);
+ // Reaching Def to an offset register can't be a phi.
+ if ((OffsetRegDN.Addr->getFlags() & NodeAttrs::PhiRef) &&
+ MI->getParent() != UseMI->getParent())
+ return false;
+
+ const MCInstrDesc &UseMID = UseMI->getDesc();
+ if ((!UseMID.mayLoad() && !UseMID.mayStore()) ||
+ HII->getAddrMode(UseMI) != HexagonII::BaseImmOffset ||
+ getBaseWithLongOffset(UseMI) < 0)
+ return false;
+
+ // Addasl output can't be a store value.
+ if (UseMID.mayStore() && UseMI->getOperand(2).isReg() &&
+ UseMI->getOperand(2).getReg() == MI->getOperand(0).getReg())
+ return false;
+
+ for (auto &Mo : UseMI->operands())
+ if (Mo.isFI())
+ return false;
+ }
+ return true;
+}
+
+bool HexagonOptAddrMode::allValidCandidates(NodeAddr<StmtNode *> SA,
+ NodeList &UNodeList) {
+ for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
+ NodeAddr<UseNode *> UN = *I;
+ RegisterRef UR = UN.Addr->getRegRef();
+ NodeSet Visited, Defs;
+ const auto &ReachingDefs = LV->getAllReachingDefsRec(UR, UN, Visited, Defs);
+ if (ReachingDefs.size() > 1) {
+ DEBUG(dbgs() << "*** Multiple Reaching Defs found!!! *** \n");
+ for (auto DI : ReachingDefs) {
+ NodeAddr<UseNode *> DA = DFG->addr<UseNode *>(DI);
+ NodeAddr<StmtNode *> tempIA = DA.Addr->getOwner(*DFG);
+ DEBUG(dbgs() << "\t\t[Reaching Def]: "
+ << Print<NodeAddr<InstrNode *>>(tempIA, *DFG) << "\n");
+ }
+ return false;
+ }
+ }
+ return true;
+}
+
+void HexagonOptAddrMode::getAllRealUses(NodeAddr<StmtNode *> SA,
+ NodeList &UNodeList) {
+ for (NodeAddr<DefNode *> DA : SA.Addr->members_if(DFG->IsDef, *DFG)) {
+ DEBUG(dbgs() << "\t\t[DefNode]: " << Print<NodeAddr<DefNode *>>(DA, *DFG)
+ << "\n");
+ RegisterRef DR = DA.Addr->getRegRef();
+ auto UseSet = LV->getAllReachedUses(DR, DA);
+
+ for (auto UI : UseSet) {
+ NodeAddr<UseNode *> UA = DFG->addr<UseNode *>(UI);
+ NodeAddr<StmtNode *> tempIA = UA.Addr->getOwner(*DFG);
+ DEBUG(dbgs() << "\t\t\t[Reached Use]: "
+ << Print<NodeAddr<InstrNode *>>(tempIA, *DFG) << "\n");
+
+ if (UA.Addr->getFlags() & NodeAttrs::PhiRef) {
+ NodeAddr<PhiNode *> PA = UA.Addr->getOwner(*DFG);
+ NodeId id = PA.Id;
+ const Liveness::RefMap &phiUse = LV->getRealUses(id);
+ DEBUG(dbgs() << "\t\t\t\tphi real Uses"
+ << Print<Liveness::RefMap>(phiUse, *DFG) << "\n");
+ if (phiUse.size() > 0) {
+ for (auto I : phiUse) {
+ if (DR != I.first)
+ continue;
+ auto phiUseSet = I.second;
+ for (auto phiUI : phiUseSet) {
+ NodeAddr<UseNode *> phiUA = DFG->addr<UseNode *>(phiUI);
+ UNodeList.push_back(phiUA);
+ }
+ }
+ }
+ } else
+ UNodeList.push_back(UA);
+ }
+ }
+}
+
+bool HexagonOptAddrMode::analyzeUses(unsigned tfrDefR,
+ const NodeList &UNodeList,
+ InstrEvalMap &InstrEvalResult,
+ short &SizeInc) {
+ bool KeepTfr = false;
+ bool HasRepInstr = false;
+ InstrEvalResult.clear();
+
+ for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
+ bool CanBeReplaced = false;
+ NodeAddr<UseNode *> UN = *I;
+ NodeAddr<StmtNode *> SN = UN.Addr->getOwner(*DFG);
+ MachineInstr *MI = SN.Addr->getCode();
+ const MCInstrDesc &MID = MI->getDesc();
+ if ((MID.mayLoad() || MID.mayStore())) {
+ if (!hasRepForm(MI, tfrDefR)) {
+ KeepTfr = true;
+ continue;
+ }
+ SizeInc++;
+ CanBeReplaced = true;
+ } else if (MI->getOpcode() == Hexagon::S2_addasl_rrri) {
+ NodeList AddaslUseList;
+
+ DEBUG(dbgs() << "\nGetting ReachedUses for === " << *MI << "\n");
+ getAllRealUses(SN, AddaslUseList);
+ // Process phi nodes.
+ if (allValidCandidates(SN, AddaslUseList) &&
+ canRemoveAddasl(SN, MI, AddaslUseList)) {
+ SizeInc += AddaslUseList.size();
+ SizeInc -= 1; // Reduce size by 1 as addasl itself can be removed.
+ CanBeReplaced = true;
+ } else
+ SizeInc++;
+ } else
+ // Currently, only load/store and addasl are handled.
+ // Some other instructions to consider -
+ // A2_add -> A2_addi
+ // M4_mpyrr_addr -> M4_mpyrr_addi
+ KeepTfr = true;
+
+ InstrEvalResult[MI] = CanBeReplaced;
+ HasRepInstr |= CanBeReplaced;
+ }
+
+ // Reduce total size by 2 if original tfr can be deleted.
+ if (!KeepTfr)
+ SizeInc -= 2;
+
+ return HasRepInstr;
+}
+
+bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp,
+ unsigned ImmOpNum) {
+ bool Changed = false;
+ MachineBasicBlock *BB = OldMI->getParent();
+ auto UsePos = MachineBasicBlock::iterator(OldMI);
+ MachineBasicBlock::instr_iterator InsertPt = UsePos.getInstrIterator();
+ ++InsertPt;
+ unsigned OpStart;
+ unsigned OpEnd = OldMI->getNumOperands();
+ MachineInstrBuilder MIB;
+
+ if (ImmOpNum == 1) {
+ if (HII->getAddrMode(OldMI) == HexagonII::BaseRegOffset) {
+ short NewOpCode = HII->getBaseWithLongOffset(OldMI);
+ assert(NewOpCode >= 0 && "Invalid New opcode\n");
+ MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
+ MIB.addOperand(OldMI->getOperand(0));
+ MIB.addOperand(OldMI->getOperand(2));
+ MIB.addOperand(OldMI->getOperand(3));
+ MIB.addOperand(ImmOp);
+ OpStart = 4;
+ Changed = true;
+ } else if (HII->getAddrMode(OldMI) == HexagonII::BaseImmOffset) {
+ short NewOpCode = HII->getAbsoluteForm(OldMI);
+ assert(NewOpCode >= 0 && "Invalid New opcode\n");
+ MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode))
+ .addOperand(OldMI->getOperand(0));
+ const GlobalValue *GV = ImmOp.getGlobal();
+ int64_t Offset = ImmOp.getOffset() + OldMI->getOperand(2).getImm();
+
+ MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags());
+ OpStart = 3;
+ Changed = true;
+ } else
+ Changed = false;
+
+ DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
+ DEBUG(dbgs() << "[TO]: " << MIB << "\n");
+ } else if (ImmOpNum == 2 && OldMI->getOperand(3).getImm() == 0) {
+ short NewOpCode = HII->xformRegToImmOffset(OldMI);
+ assert(NewOpCode >= 0 && "Invalid New opcode\n");
+ MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
+ MIB.addOperand(OldMI->getOperand(0));
+ MIB.addOperand(OldMI->getOperand(1));
+ MIB.addOperand(ImmOp);
+ OpStart = 4;
+ Changed = true;
+ DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
+ DEBUG(dbgs() << "[TO]: " << MIB << "\n");
+ }
+
+ if (Changed)
+ for (unsigned i = OpStart; i < OpEnd; ++i)
+ MIB.addOperand(OldMI->getOperand(i));
+
+ return Changed;
+}
+
+bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
+ unsigned ImmOpNum) {
+ bool Changed = false;
+ unsigned OpStart;
+ unsigned OpEnd = OldMI->getNumOperands();
+ MachineBasicBlock *BB = OldMI->getParent();
+ auto UsePos = MachineBasicBlock::iterator(OldMI);
+ MachineBasicBlock::instr_iterator InsertPt = UsePos.getInstrIterator();
+ ++InsertPt;
+ MachineInstrBuilder MIB;
+ if (ImmOpNum == 0) {
+ if (HII->getAddrMode(OldMI) == HexagonII::BaseRegOffset) {
+ short NewOpCode = HII->getBaseWithLongOffset(OldMI);
+ assert(NewOpCode >= 0 && "Invalid New opcode\n");
+ MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
+ MIB.addOperand(OldMI->getOperand(1));
+ MIB.addOperand(OldMI->getOperand(2));
+ MIB.addOperand(ImmOp);
+ MIB.addOperand(OldMI->getOperand(3));
+ OpStart = 4;
+ } else if (HII->getAddrMode(OldMI) == HexagonII::BaseImmOffset) {
+ short NewOpCode = HII->getAbsoluteForm(OldMI);
+ assert(NewOpCode >= 0 && "Invalid New opcode\n");
+ MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
+ const GlobalValue *GV = ImmOp.getGlobal();
+ int64_t Offset = ImmOp.getOffset() + OldMI->getOperand(1).getImm();
+ MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags());
+ MIB.addOperand(OldMI->getOperand(2));
+ OpStart = 3;
+ }
+ Changed = true;
+ DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
+ DEBUG(dbgs() << "[TO]: " << MIB << "\n");
+ } else if (ImmOpNum == 1 && OldMI->getOperand(2).getImm() == 0) {
+ short NewOpCode = HII->xformRegToImmOffset(OldMI);
+ assert(NewOpCode >= 0 && "Invalid New opcode\n");
+ MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
+ MIB.addOperand(OldMI->getOperand(0));
+ MIB.addOperand(ImmOp);
+ MIB.addOperand(OldMI->getOperand(1));
+ OpStart = 2;
+ Changed = true;
+ DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
+ DEBUG(dbgs() << "[TO]: " << MIB << "\n");
+ }
+ if (Changed)
+ for (unsigned i = OpStart; i < OpEnd; ++i)
+ MIB.addOperand(OldMI->getOperand(i));
+
+ return Changed;
+}
+
+short HexagonOptAddrMode::getBaseWithLongOffset(const MachineInstr *MI) const {
+ if (HII->getAddrMode(MI) == HexagonII::BaseImmOffset) {
+ short TempOpCode = HII->getBaseWithRegOffset(MI);
+ return HII->getBaseWithLongOffset(TempOpCode);
+ } else
+ return HII->getBaseWithLongOffset(MI);
+}
+
+bool HexagonOptAddrMode::changeAddAsl(NodeAddr<UseNode *> AddAslUN,
+ MachineInstr *AddAslMI,
+ const MachineOperand &ImmOp,
+ unsigned ImmOpNum) {
+ NodeAddr<StmtNode *> SA = AddAslUN.Addr->getOwner(*DFG);
+
+ DEBUG(dbgs() << "Processing addasl :" << *AddAslMI << "\n");
+
+ NodeList UNodeList;
+ getAllRealUses(SA, UNodeList);
+
+ for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
+ NodeAddr<UseNode *> UseUN = *I;
+ assert(!(UseUN.Addr->getFlags() & NodeAttrs::PhiRef) &&
+ "Can't transform this 'AddAsl' instruction!");
+
+ NodeAddr<StmtNode *> UseIA = UseUN.Addr->getOwner(*DFG);
+ DEBUG(dbgs() << "[InstrNode]: " << Print<NodeAddr<InstrNode *>>(UseIA, *DFG)
+ << "\n");
+ MachineInstr *UseMI = UseIA.Addr->getCode();
+ DEBUG(dbgs() << "[MI <BB#" << UseMI->getParent()->getNumber()
+ << ">]: " << *UseMI << "\n");
+ const MCInstrDesc &UseMID = UseMI->getDesc();
+ assert(HII->getAddrMode(UseMI) == HexagonII::BaseImmOffset);
+
+ auto UsePos = MachineBasicBlock::iterator(UseMI);
+ MachineBasicBlock::instr_iterator InsertPt = UsePos.getInstrIterator();
+ short NewOpCode = getBaseWithLongOffset(UseMI);
+ assert(NewOpCode >= 0 && "Invalid New opcode\n");
+
+ unsigned OpStart;
+ unsigned OpEnd = UseMI->getNumOperands();
+
+ MachineBasicBlock *BB = UseMI->getParent();
+ MachineInstrBuilder MIB =
+ BuildMI(*BB, InsertPt, UseMI->getDebugLoc(), HII->get(NewOpCode));
+ // change mem(Rs + # ) -> mem(Rt << # + ##)
+ if (UseMID.mayLoad()) {
+ MIB.addOperand(UseMI->getOperand(0));
+ MIB.addOperand(AddAslMI->getOperand(2));
+ MIB.addOperand(AddAslMI->getOperand(3));
+ const GlobalValue *GV = ImmOp.getGlobal();
+ MIB.addGlobalAddress(GV, UseMI->getOperand(2).getImm(),
+ ImmOp.getTargetFlags());
+ OpStart = 3;
+ } else if (UseMID.mayStore()) {
+ MIB.addOperand(AddAslMI->getOperand(2));
+ MIB.addOperand(AddAslMI->getOperand(3));
+ const GlobalValue *GV = ImmOp.getGlobal();
+ MIB.addGlobalAddress(GV, UseMI->getOperand(1).getImm(),
+ ImmOp.getTargetFlags());
+ MIB.addOperand(UseMI->getOperand(2));
+ OpStart = 3;
+ } else
+ llvm_unreachable("Unhandled instruction");
+
+ for (unsigned i = OpStart; i < OpEnd; ++i)
+ MIB.addOperand(UseMI->getOperand(i));
+
+ Deleted.insert(UseMI);
+ }
+
+ return true;
+}
+
+bool HexagonOptAddrMode::xformUseMI(MachineInstr *TfrMI, MachineInstr *UseMI,
+ NodeAddr<UseNode *> UseN,
+ unsigned UseMOnum) {
+ const MachineOperand ImmOp = TfrMI->getOperand(1);
+ const MCInstrDesc &MID = UseMI->getDesc();
+ unsigned Changed = false;
+ if (MID.mayLoad())
+ Changed = changeLoad(UseMI, ImmOp, UseMOnum);
+ else if (MID.mayStore())
+ Changed = changeStore(UseMI, ImmOp, UseMOnum);
+ else if (UseMI->getOpcode() == Hexagon::S2_addasl_rrri)
+ Changed = changeAddAsl(UseN, UseMI, ImmOp, UseMOnum);
+
+ if (Changed)
+ Deleted.insert(UseMI);
+
+ return Changed;
+}
+
+bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) {
+ bool Changed = false;
+
+ for (auto IA : BA.Addr->members(*DFG)) {
+ if (!DFG->IsCode<NodeAttrs::Stmt>(IA))
+ continue;
+
+ NodeAddr<StmtNode *> SA = IA;
+ MachineInstr *MI = SA.Addr->getCode();
+ if (MI->getOpcode() != Hexagon::A2_tfrsi ||
+ !MI->getOperand(1).isGlobal())
+ continue;
+
+ DEBUG(dbgs() << "[Analyzing A2_tfrsi]: " << *MI << "\n");
+ DEBUG(dbgs() << "\t[InstrNode]: " << Print<NodeAddr<InstrNode *>>(IA, *DFG)
+ << "\n");
+
+ NodeList UNodeList;
+ getAllRealUses(SA, UNodeList);
+
+ if (!allValidCandidates(SA, UNodeList))
+ continue;
+
+ short SizeInc = 0;
+ unsigned DefR = MI->getOperand(0).getReg();
+ InstrEvalMap InstrEvalResult;
+
+ // Analyze all uses and calculate increase in size. Perform the optimization
+ // only if there is no increase in size.
+ if (!analyzeUses(DefR, UNodeList, InstrEvalResult, SizeInc))
+ continue;
+ if (SizeInc > CodeGrowthLimit)
+ continue;
+
+ bool KeepTfr = false;
+
+ DEBUG(dbgs() << "\t[Total reached uses] : " << UNodeList.size() << "\n");
+ DEBUG(dbgs() << "\t[Processing Reached Uses] ===\n");
+ for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
+ NodeAddr<UseNode *> UseN = *I;
+ assert(!(UseN.Addr->getFlags() & NodeAttrs::PhiRef) &&
+ "Found a PhiRef node as a real reached use!!");
+
+ NodeAddr<StmtNode *> OwnerN = UseN.Addr->getOwner(*DFG);
+ MachineInstr *UseMI = OwnerN.Addr->getCode();
+ unsigned BBNum = UseMI->getParent()->getNumber();
+ DEBUG(dbgs() << "\t\t[MI <BB#" << BBNum << ">]: " << *UseMI << "\n");
+
+ int UseMOnum = -1;
+ unsigned NumOperands = UseMI->getNumOperands();
+ for (unsigned j = 0; j < NumOperands - 1; ++j) {
+ const MachineOperand &op = UseMI->getOperand(j);
+ if (op.isReg() && op.isUse() && DefR == op.getReg())
+ UseMOnum = j;
+ }
+ assert(UseMOnum >= 0 && "Invalid reached use!");
+
+ if (InstrEvalResult[UseMI])
+ // Change UseMI if replacement is possible.
+ Changed |= xformUseMI(MI, UseMI, UseN, UseMOnum);
+ else
+ KeepTfr = true;
+ }
+ if (!KeepTfr)
+ Deleted.insert(MI);
+ }
+ return Changed;
+}
+
+void HexagonOptAddrMode::updateMap(NodeAddr<InstrNode *> IA) {
+ RegisterSet RRs;
+ for (NodeAddr<RefNode *> RA : IA.Addr->members(*DFG))
+ RRs.insert(RA.Addr->getRegRef());
+ bool Common = false;
+ for (auto &R : RDefMap) {
+ if (!RRs.count(R.first))
+ continue;
+ Common = true;
+ break;
+ }
+ if (!Common)
+ return;
+
+ for (auto &R : RDefMap) {
+ auto F = DefM.find(R.first);
+ if (F == DefM.end() || F->second.empty())
+ continue;
+ R.second[IA.Id] = F->second.top()->Id;
+ }
+}
+
+bool HexagonOptAddrMode::constructDefMap(MachineBasicBlock *B) {
+ bool Changed = false;
+ auto BA = DFG->getFunc().Addr->findBlock(B, *DFG);
+ DFG->markBlock(BA.Id, DefM);
+
+ for (NodeAddr<InstrNode *> IA : BA.Addr->members(*DFG)) {
+ updateMap(IA);
+ DFG->pushDefs(IA, DefM);
+ }
+
+ MachineDomTreeNode *N = MDT->getNode(B);
+ for (auto I : *N)
+ Changed |= constructDefMap(I->getBlock());
+
+ DFG->releaseBlock(BA.Id, DefM);
+ return Changed;
+}
+
+bool HexagonOptAddrMode::runOnMachineFunction(MachineFunction &MF) {
+ bool Changed = false;
+ auto &HST = MF.getSubtarget<HexagonSubtarget>();
+ auto &MRI = MF.getRegInfo();
+ HII = HST.getInstrInfo();
+ const auto &MDF = getAnalysis<MachineDominanceFrontier>();
+ MDT = &getAnalysis<MachineDominatorTree>();
+ const auto &TRI = *MF.getSubtarget().getRegisterInfo();
+ const TargetOperandInfo TOI(*HII);
+
+ RegisterAliasInfo RAI(TRI);
+ DataFlowGraph G(MF, *HII, TRI, *MDT, MDF, RAI, TOI);
+ G.build();
+ DFG = &G;
+
+ Liveness L(MRI, *DFG);
+ L.computePhiInfo();
+ LV = &L;
+
+ constructDefMap(&DFG->getMF().front());
+
+ Deleted.clear();
+ NodeAddr<FuncNode *> FA = DFG->getFunc();
+ DEBUG(dbgs() << "==== [RefMap#]=====:\n "
+ << Print<NodeAddr<FuncNode *>>(FA, *DFG) << "\n");
+
+ for (NodeAddr<BlockNode *> BA : FA.Addr->members(*DFG))
+ Changed |= processBlock(BA);
+
+ for (auto MI : Deleted)
+ MI->eraseFromParent();
+
+ if (Changed) {
+ G.build();
+ L.computeLiveIns();
+ L.resetLiveIns();
+ L.resetKills();
+ }
+
+ return Changed;
+}
+
+//===----------------------------------------------------------------------===//
+// Public Constructor Functions
+//===----------------------------------------------------------------------===//
+
+FunctionPass *llvm::createHexagonOptAddrMode() {
+ return new HexagonOptAddrMode();
+}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp?rev=268051&r1=268050&r2=268051&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp Fri Apr 29 10:49:13 2016
@@ -33,6 +33,10 @@ static cl::opt<bool> EnableRDFOpt("rdf-o
static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
+static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
+ cl::Hidden, cl::ZeroOrMore, cl::init(false),
+ cl::desc("Disable Hexagon Addressing Mode Optimization"));
+
static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
cl::Hidden, cl::ZeroOrMore, cl::init(false),
cl::desc("Disable Hexagon CFG Optimization"));
@@ -113,6 +117,7 @@ namespace llvm {
FunctionPass *createHexagonLoopRescheduling();
FunctionPass *createHexagonNewValueJump();
FunctionPass *createHexagonOptimizeSZextends();
+ FunctionPass *createHexagonOptAddrMode();
FunctionPass *createHexagonPacketizer();
FunctionPass *createHexagonPeephole();
FunctionPass *createHexagonRDFOpt();
@@ -272,6 +277,8 @@ void HexagonPassConfig::addPostRegAlloc(
addPass(createHexagonRDFOpt());
if (!DisableHexagonCFGOpt)
addPass(createHexagonCFGOptimizer(), false);
+ if (!DisableAModeOpt)
+ addPass(createHexagonOptAddrMode(), false);
}
}
Modified: llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp?rev=268051&r1=268050&r2=268051&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp Fri Apr 29 10:49:13 2016
@@ -235,7 +235,93 @@ NodeList Liveness::getAllReachingDefs(No
}
+NodeSet Liveness::getAllReachingDefsRec(RegisterRef RefRR,
+ NodeAddr<RefNode*> RefA, NodeSet &Visited, const NodeSet &Defs) {
+ // Collect all defined registers. Do not consider phis to be defining
+ // anything, only collect "real" definitions.
+ RegisterSet DefRRs;
+ for (const auto D : Defs) {
+ const auto DA = DFG.addr<const DefNode*>(D);
+ if (!(DA.Addr->getFlags() & NodeAttrs::PhiRef))
+ DefRRs.insert(DA.Addr->getRegRef());
+ }
+
+ auto RDs = getAllReachingDefs(RefRR, RefA, true, DefRRs);
+ if (RDs.empty())
+ return Defs;
+
+ // Make a copy of the preexisting definitions and add the newly found ones.
+ NodeSet TmpDefs = Defs;
+ for (auto R : RDs)
+ TmpDefs.insert(R.Id);
+
+ NodeSet Result = Defs;
+
+ for (NodeAddr<DefNode*> DA : RDs) {
+ Result.insert(DA.Id);
+ if (!(DA.Addr->getFlags() & NodeAttrs::PhiRef))
+ continue;
+ NodeAddr<PhiNode*> PA = DA.Addr->getOwner(DFG);
+ if (Visited.count(PA.Id))
+ continue;
+ Visited.insert(PA.Id);
+ // Go over all phi uses and get the reaching defs for each use.
+ for (auto U : PA.Addr->members_if(DFG.IsRef<NodeAttrs::Use>, DFG)) {
+ const auto &T = getAllReachingDefsRec(RefRR, U, Visited, TmpDefs);
+ Result.insert(T.begin(), T.end());
+ }
+ }
+
+ return Result;
+}
+
+
+NodeSet Liveness::getAllReachedUses(RegisterRef RefRR,
+ NodeAddr<DefNode*> DefA, const RegisterSet &DefRRs) {
+ NodeSet Uses;
+
+ // If the original register is already covered by all the intervening
+ // defs, no more uses can be reached.
+ if (RAI.covers(DefRRs, RefRR))
+ return Uses;
+
+ // Add all directly reached uses.
+ NodeId U = DefA.Addr->getReachedUse();
+ while (U != 0) {
+ auto UA = DFG.addr<UseNode*>(U);
+ auto UR = UA.Addr->getRegRef();
+ if (RAI.alias(RefRR, UR) && !RAI.covers(DefRRs, UR))
+ Uses.insert(U);
+ U = UA.Addr->getSibling();
+ }
+
+ // Traverse all reached defs.
+ for (NodeId D = DefA.Addr->getReachedDef(), NextD; D != 0; D = NextD) {
+ auto DA = DFG.addr<DefNode*>(D);
+ NextD = DA.Addr->getSibling();
+ auto DR = DA.Addr->getRegRef();
+ // If this def is already covered, it cannot reach anything new.
+ // Similarly, skip it if it is not aliased to the interesting register.
+ if (RAI.covers(DefRRs, DR) || !RAI.alias(RefRR, DR))
+ continue;
+ NodeSet T;
+ if (DA.Addr->getFlags() & NodeAttrs::Preserving) {
+ // If it is a preserving def, do not update the set of intervening defs.
+ T = getAllReachedUses(RefRR, DA, DefRRs);
+ } else {
+ RegisterSet NewDefRRs = DefRRs;
+ NewDefRRs.insert(DR);
+ T = getAllReachedUses(RefRR, DA, NewDefRRs);
+ }
+ Uses.insert(T.begin(), T.end());
+ }
+ return Uses;
+}
+
+
void Liveness::computePhiInfo() {
+ RealUseMap.clear();
+
NodeList Phis;
NodeAddr<FuncNode*> FA = DFG.getFunc();
auto Blocks = FA.Addr->members(DFG);
Modified: llvm/trunk/lib/Target/Hexagon/RDFLiveness.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/RDFLiveness.h?rev=268051&r1=268050&r2=268051&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/RDFLiveness.h (original)
+++ llvm/trunk/lib/Target/Hexagon/RDFLiveness.h Fri Apr 29 10:49:13 2016
@@ -41,6 +41,10 @@ namespace rdf {
NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr<RefNode*> RefA,
bool FullChain = false, const RegisterSet &DefRRs = RegisterSet());
NodeList getAllReachingDefs(NodeAddr<RefNode*> RefA);
+ NodeSet getAllReachingDefsRec(RegisterRef RefRR, NodeAddr<RefNode*> RefA,
+ NodeSet &Visited, const NodeSet &Defs);
+ NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr<DefNode*> DefA,
+ const RegisterSet &DefRRs = RegisterSet());
LiveMapType &getLiveMap() { return LiveMap; }
const LiveMapType &getLiveMap() const { return LiveMap; }
Added: llvm/trunk/test/CodeGen/Hexagon/opt-addr-mode.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/opt-addr-mode.ll?rev=268051&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/opt-addr-mode.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/opt-addr-mode.ll Fri Apr 29 10:49:13 2016
@@ -0,0 +1,107 @@
+; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 -disable-hexagon-amodeopt < %s | FileCheck %s --check-prefix=CHECK-NO-AMODE
+; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 -disable-hexagon-amodeopt=0 -hexagon-amode-growth-limit=4 < %s | FileCheck %s --check-prefix=CHECK-AMODE
+
+; CHECK-NO-AMODE: [[REG0:(r[0-9]+)]] = ##global_2
+; CHECK-NO-AMODE: memw([[REG0]] + {{.*}}<<#2) =
+
+; CHECK-AMODE: [[REG1:(r[0-9]+)]] = memw(##global_1)
+; CHECK-AMODE: memw([[REG1]]<<#2 + ##global_2) =
+
+ at global_1 = external global i32, align 4
+ at global_2 = external global [128 x i32], align 8
+
+declare i32 @foo(i32, i32) #0
+
+define i32 @fred(i32 %a0, i32 %a1, i32* %p) #0 {
+entry:
+ %call24 = tail call i32 @foo(i32 %a0, i32 1) #0
+ %tobool26 = icmp eq i32 %call24, 0
+ br i1 %tobool26, label %while.end, label %while.body.lr.ph
+
+while.body.lr.ph: ; preds = %entry
+ %cmp3 = icmp sgt i32 %a1, 19
+ %sub = sub nsw i32 19, %a0
+ %xor = xor i32 %a0, 1
+ br i1 %cmp3, label %while.body.us.preheader, label %while.body.preheader
+
+while.body.preheader: ; preds = %while.body.lr.ph
+ br label %while.body
+
+while.body.us.preheader: ; preds = %while.body.lr.ph
+ br label %while.body.us
+
+while.body.us: ; preds = %while.body.us.preheader, %while.cond.backedge.us
+ %call27.us = phi i32 [ %call.us, %while.cond.backedge.us ], [ %call24, %while.body.us.preheader ]
+ %x0 = load i32, i32* %p, align 4, !tbaa !4
+ %cmp.us = icmp sgt i32 %x0, 0
+ br i1 %cmp.us, label %if.then.us, label %if.end.us
+
+if.then.us: ; preds = %while.body.us
+ %sext.us = shl i32 %call27.us, 24
+ %conv2.us = ashr i32 %sext.us, 24
+ %x10 = tail call i32 @foo(i32 %conv2.us, i32 %sext.us) #0
+ br label %if.end.us
+
+if.end.us: ; preds = %if.then.us, %while.body.us
+ %x1 = load i32, i32* %p, align 4, !tbaa !4
+ %call8.us = tail call i32 @foo(i32 %sub, i32 %a1) #0
+ %tobool11.us = icmp eq i32 %call8.us, 0
+ br i1 %tobool11.us, label %while.cond.backedge.us, label %if.then12.us
+
+if.then12.us: ; preds = %if.end.us
+ %x3 = load i32, i32* %p, align 4, !tbaa !4
+ %sub13.us = sub i32 %x3, %x1
+ %x4 = load i32, i32* @global_1, align 4, !tbaa !4
+ %arrayidx.us = getelementptr inbounds [128 x i32], [128 x i32]* @global_2, i32 0, i32 %x4
+ store i32 %sub13.us, i32* %arrayidx.us, align 4, !tbaa !4
+ br label %while.cond.backedge.us
+
+while.cond.backedge.us: ; preds = %if.then12.us, %if.end.us
+ %call.us = tail call i32 @foo(i32 %a0, i32 2) #0
+ %tobool.us = icmp eq i32 %call.us, 0
+ br i1 %tobool.us, label %while.end.loopexit, label %while.body.us
+
+while.body: ; preds = %while.body.preheader, %while.cond.backedge
+ %call27 = phi i32 [ %call, %while.cond.backedge ], [ %call24, %while.body.preheader ]
+ %x5 = load i32, i32* %p, align 4, !tbaa !4
+ %cmp = icmp sgt i32 %x5, 0
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %while.body
+ %sext = shl i32 %call27, 24
+ %conv2 = ashr i32 %sext, 24
+ %x11 = tail call i32 @foo(i32 %conv2, i32 %sext) #0
+ br label %if.end
+
+if.end: ; preds = %if.then, %while.body
+ %tobool11 = icmp eq i32 %call27, 0
+ br i1 %tobool11, label %while.cond.backedge, label %if.then12
+
+if.then12: ; preds = %if.end
+ %x7 = load i32, i32* @global_1, align 4, !tbaa !4
+ %arrayidx = getelementptr inbounds [128 x i32], [128 x i32]* @global_2, i32 0, i32 %x7
+ store i32 0, i32* %arrayidx, align 4, !tbaa !4
+ br label %while.cond.backedge
+
+while.cond.backedge: ; preds = %if.then12, %if.end
+ %call = tail call i32 @foo(i32 %a0, i32 3) #0
+ %tobool = icmp eq i32 %call, 0
+ br i1 %tobool, label %while.end.loopexit33, label %while.body
+
+while.end.loopexit: ; preds = %while.cond.backedge.us
+ br label %while.end
+
+while.end.loopexit33: ; preds = %while.cond.backedge
+ br label %while.end
+
+while.end: ; preds = %while.end.loopexit33, %while.end.loopexit, %entry
+ ret i32 0
+}
+
+attributes #0 = { nounwind }
+
+!1 = !{!2, !2, i64 0}
+!2 = !{!"omnipotent char", !3, i64 0}
+!3 = !{!"Simple C/C++ TBAA"}
+!4 = !{!5, !5, i64 0}
+!5 = !{!"int", !2, i64 0}
Modified: llvm/trunk/test/CodeGen/Hexagon/tls_pic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/tls_pic.ll?rev=268051&r1=268050&r2=268051&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/tls_pic.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/tls_pic.ll Fri Apr 29 10:49:13 2016
@@ -1,10 +1,10 @@
-; RUN: llc -O2 -march=hexagon -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -O0 -march=hexagon -relocation-model=pic < %s | FileCheck %s
@dst_ie = thread_local(initialexec) global i32 0, align 4
@src_ie = thread_local(initialexec) global i32 0, align 4
; CHECK-LABEL: test_initial_exec
-; CHECK: = add(pc, ##_GLOBAL_OFFSET_TABLE_ at PCREL)
+; CHECK-DAG: = add(pc, ##_GLOBAL_OFFSET_TABLE_ at PCREL)
; CHECK-DAG: = ##src_ie at IEGOT
; CHECK-DAG: = ##dst_ie at IEGOT
; CHECK-NOT: call
@@ -22,7 +22,7 @@ entry:
; general-dynamic model.
; CHECK-LABEL: test_dynamic
-; CHECK: = add(pc, ##_GLOBAL_OFFSET_TABLE_ at PCREL)
+; CHECK-DAG: = add(pc, ##_GLOBAL_OFFSET_TABLE_ at PCREL)
; CHECK-DAG: = ##src_gd at GDGOT
; CHECK-DAG: = ##dst_gd at GDGOT
; CHECK-DAG: call src_gd at GDPLT
Modified: llvm/trunk/test/CodeGen/Hexagon/tls_static.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/tls_static.ll?rev=268051&r1=268050&r2=268051&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/tls_static.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/tls_static.ll Fri Apr 29 10:49:13 2016
@@ -1,4 +1,4 @@
-; RUN: llc -O2 -march=hexagon -relocation-model=static < %s | FileCheck %s
+; RUN: llc -O0 -march=hexagon -relocation-model=static < %s | FileCheck %s
@dst_le = thread_local global i32 0, align 4
@src_le = thread_local global i32 0, align 4
Modified: llvm/trunk/test/CodeGen/Hexagon/zextloadi1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/zextloadi1.ll?rev=268051&r1=268050&r2=268051&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/zextloadi1.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/zextloadi1.ll Fri Apr 29 10:49:13 2016
@@ -1,23 +1,28 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
-
-; CHECK: r{{[0-9]+}} = ##i129_l+16
-; CHECK: r{{[0-9]+}} = ##i129_s+16
-; CHECK: memd(##i129_s) = r{{[0-9]+:[0-9]+}}
-; CHECK: r{{[0-9]+}} = ##i65_l+8
-; CHECK: r{{[0-9]+}} = ##i65_s+8
-; CHECK: memd(##i65_s) = r{{[0-9]+:[0-9]+}}
+; RUN: llc -march=hexagon < %s | FileCheck %s
@i65_l = external global i65
@i65_s = external global i65
@i129_l = external global i129
@i129_s = external global i129
+; CHECK-LABEL: i129_ls
+; CHECK-DAG: r[[REG0:[0-9:]+]] = memd(##i129_l)
+; CHECK-DAG: r[[REG1:[0-9:]+]] = memd(##i129_l+8)
+; CHECK-DAG: r[[REG2:[0-9]+]] = memub(##i129_l+16)
+; CHECK-DAG: memb(##i129_s+16) = r[[REG2]]
+; CHECK-DAG: memd(##i129_s+8) = r[[REG1]]
+; CHECK-DAG: memd(##i129_s) = r[[REG0]]
define void @i129_ls() nounwind {
%tmp = load i129, i129* @i129_l
store i129 %tmp, i129* @i129_s
ret void
}
+; CHECK-LABEL: i65_ls
+; CHECK-DAG: r[[REG0:[0-9:]+]] = memd(##i65_l)
+; CHECK-DAG: r[[REG1:[0-9]+]] = memub(##i65_l+8)
+; CHECK-DAG: memd(##i65_s) = r[[REG0]]
+; CHECK-DAG: memb(##i65_s+8) = r[[REG1]]
define void @i65_ls() nounwind {
%tmp = load i65, i65* @i65_l
store i65 %tmp, i65* @i65_s
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