[llvm] r267693 - [mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions
Zlatko Buljan via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 27 04:02:24 PDT 2016
Author: zbuljan
Date: Wed Apr 27 06:02:23 2016
New Revision: 267693
URL: http://llvm.org/viewvc/llvm-project?rev=267693&view=rev
Log:
[mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions
Differential Revision: http://reviews.llvm.org/D17989
Modified:
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll
llvm/trunk/test/CodeGen/Mips/micromips-shift.ll
llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt
llvm/trunk/test/MC/Mips/micromips-shift-instructions.s
llvm/trunk/test/MC/Mips/micromips/invalid.s
llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
llvm/trunk/test/MC/Mips/micromips64r6/invalid.s
llvm/trunk/test/MC/Mips/micromips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=267693&r1=267692&r2=267693&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Wed Apr 27 06:02:23 2016
@@ -981,18 +981,18 @@ class SLL16_MMR6_DESC : ShiftIMM16<"sll1
MMR6Arch<"sll16">;
class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
MMR6Arch<"srl16">;
-class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"srl16">,
+class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"break16">,
MicroMipsR6Inst16;
class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>,
- MMR6Arch<"srl16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
-class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"srl16">,
+ MMR6Arch<"li16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
+class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">,
MicroMipsR6Inst16;
class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">,
MicroMipsR6Inst16;
class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
- MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
+ MMR6Arch<"subu16">, MicroMipsR6Inst16;
class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
- MMR6Arch<"sdbbp16">;
+ MMR6Arch<"xor16">;
class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
dag OutOperandList = (outs GPR32Opnd:$rt);
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=267693&r1=267692&r2=267693&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Wed Apr 27 06:02:23 2016
@@ -972,11 +972,20 @@ def : MipsPat<(shl GPRMM16:$src, immZExt
(SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
(SLL_MM GPR32:$src, immZExt5:$imm)>;
+def : MipsPat<(shl GPR32:$lhs, GPR32:$rhs),
+ (SLLV_MM GPR32:$lhs, GPR32:$rhs)>;
def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
(SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
(SRL_MM GPR32:$src, immZExt5:$imm)>;
+def : MipsPat<(srl GPR32:$lhs, GPR32:$rhs),
+ (SRLV_MM GPR32:$lhs, GPR32:$rhs)>;
+
+def : MipsPat<(sra GPR32:$src, immZExt5:$imm),
+ (SRA_MM GPR32:$src, immZExt5:$imm)>;
+def : MipsPat<(sra GPR32:$lhs, GPR32:$rhs),
+ (SRAV_MM GPR32:$lhs, GPR32:$rhs)>;
def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
(SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>;
@@ -1023,4 +1032,22 @@ def : MipsInstAlias<"tltu $rs, $rt",
(TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tne $rs, $rt",
(TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+def : MipsInstAlias<"sll $rd, $rt, $rs",
+ (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+def : MipsInstAlias<"sra $rd, $rt, $rs",
+ (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+def : MipsInstAlias<"srl $rd, $rt, $rs",
+ (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+def : MipsInstAlias<"sll $rd, $rt",
+ (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
+def : MipsInstAlias<"sra $rd, $rt",
+ (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
+def : MipsInstAlias<"srl $rd, $rt",
+ (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
+def : MipsInstAlias<"sll $rd, $shamt",
+ (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
+def : MipsInstAlias<"sra $rd, $shamt",
+ (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
+def : MipsInstAlias<"srl $rd, $shamt",
+ (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
}
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=267693&r1=267692&r2=267693&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Apr 27 06:02:23 2016
@@ -1694,7 +1694,6 @@ def SLL : MMRel, shift_rotate_imm<"sll"
immZExt5>, SRA_FM<0, 0>;
def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
immZExt5>, SRA_FM<2, 0>;
-}
def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
immZExt5>, SRA_FM<3, 0>;
def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
@@ -1703,6 +1702,7 @@ def SRLV : MMRel, shift_rotate_reg<"srlv
SRLV_FM<6, 0>;
def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
SRLV_FM<7, 0>;
+}
// Rotate Instructions
def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
@@ -2246,8 +2246,6 @@ let AdditionalPredicates = [NotInMicroMi
def : MipsInstAlias<"tne $rs, $rt",
(TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
}
-def : MipsInstAlias<"sll $rd, $rt, $rs",
- (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"sub, $rd, $rs, $imm",
(ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
@@ -2259,10 +2257,14 @@ def : MipsInstAlias<"subu, $rd, $rs, $im
InvertedImOperand:$imm), 0>;
def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
InvertedImOperand:$imm), 0>;
-def : MipsInstAlias<"sra $rd, $rt, $rs",
- (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
-def : MipsInstAlias<"srl $rd, $rt, $rs",
- (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+let AdditionalPredicates = [NotInMicroMips] in {
+ def : MipsInstAlias<"sll $rd, $rt, $rs",
+ (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+ def : MipsInstAlias<"sra $rd, $rt, $rs",
+ (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+ def : MipsInstAlias<"srl $rd, $rt, $rs",
+ (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+}
def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
def : MipsInstAlias<"sync",
(SYNC 0), 1>, ISA_MIPS2;
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll?rev=267693&r1=267692&r2=267693&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll Wed Apr 27 06:02:23 2016
@@ -37,6 +37,10 @@
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
; RUN: -check-prefix=64R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MMR3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MMR6
define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -53,7 +57,9 @@ entry:
; ALL-LABEL: ashr_i8:
; FIXME: The andi instruction is redundant.
- ; ALL: andi $[[T0:[0-9]+]], $5, 255
+ ; GP32: andi $[[T0:[0-9]+]], $5, 255
+ ; GP64: andi $[[T0:[0-9]+]], $5, 255
+ ; MM: andi16 $[[T0:[0-9]+]], $5, 255
; ALL: srav $2, $4, $[[T0]]
%r = ashr i8 %a, %b
@@ -65,7 +71,9 @@ entry:
; ALL-LABEL: ashr_i16:
; FIXME: The andi instruction is redundant.
- ; ALL: andi $[[T0:[0-9]+]], $5, 65535
+ ; GP32: andi $[[T0:[0-9]+]], $5, 65535
+ ; GP64: andi $[[T0:[0-9]+]], $5, 65535
+ ; MM: andi16 $[[T0:[0-9]+]], $5, 65535
; ALL: srav $2, $4, $[[T0]]
%r = ashr i16 %a, %b
@@ -133,6 +141,32 @@ entry:
; GP64: dsrav $2, $4, $5
+ ; MMR3: srlv $[[T0:[0-9]+]], $5, $7
+ ; MMR3: sll16 $[[T1:[0-9]+]], $4, 1
+ ; MMR3: not16 $[[T2:[0-9]+]], $7
+ ; MMR3: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
+ ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]]
+ ; MMR3: srav $[[T5:[0-9]+]], $4, $7
+ ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32
+ ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]]
+ ; MMR3: sra $[[T8:[0-9]+]], $4, 31
+ ; MMR3: movn $2, $[[T8]], $[[T6]]
+
+ ; MMR6: srav $[[T0:[0-9]+]], $4, $7
+ ; MMR6: andi16 $[[T1:[0-9]+]], $7, 32
+ ; MMR6: seleqz $[[T2:[0-9]+]], $[[T0]], $[[T1]]
+ ; MMR6: sra $[[T3:[0-9]+]], $4, 31
+ ; MMR6: selnez $[[T4:[0-9]+]], $[[T3]], $[[T1]]
+ ; MMR6: or $[[T5:[0-9]+]], $[[T4]], $[[T2]]
+ ; MMR6: srlv $[[T6:[0-9]+]], $5, $7
+ ; MMR6: not $[[T7:[0-9]+]], $7
+ ; MMR6: sll16 $[[T8:[0-9]+]], $4, 1
+ ; MMR6: sllv $[[T9:[0-9]+]], $[[T8]], $[[T7]]
+ ; MMR6: or16 $[[T10:[0-9]+]], $[[T6]]
+ ; MMR6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]]
+ ; MMR6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]]
+ ; MMR6: or $3, $[[T12]], $[[T11]]
+
%r = ashr i64 %a, %b
ret i64 %r
}
@@ -192,6 +226,8 @@ entry:
; 64R6: jr $ra
; 64R6: or $3, $[[T13]], $[[T12]]
+ ; MM: lw $25, %call16(__ashrti3)($2)
+
%r = ashr i128 %a, %b
ret i128 %r
}
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll?rev=267693&r1=267692&r2=267693&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll Wed Apr 27 06:02:23 2016
@@ -37,6 +37,10 @@
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
; RUN: -check-prefix=64R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MMR3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MMR6
define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -53,7 +57,9 @@ entry:
; ALL-LABEL: lshr_i8:
; ALL: srlv $[[T0:[0-9]+]], $4, $5
- ; ALL: andi $2, $[[T0]], 255
+ ; GP32: andi $2, $[[T0]], 255
+ ; GP64: andi $2, $[[T0]], 255
+ ; MM: andi16 $2, $[[T0]], 255
%r = lshr i8 %a, %b
ret i8 %r
@@ -64,7 +70,9 @@ entry:
; ALL-LABEL: lshr_i16:
; ALL: srlv $[[T0:[0-9]+]], $4, $5
- ; ALL: andi $2, $[[T0]], 65535
+ ; GP32: andi $2, $[[T0]], 65535
+ ; GP64: andi $2, $[[T0]], 65535
+ ; MM: andi16 $2, $[[T0]], 65535
%r = lshr i16 %a, %b
ret i16 %r
@@ -127,6 +135,29 @@ entry:
; GP64: dsrlv $2, $4, $5
+ ; MMR3: srlv $[[T0:[0-9]+]], $5, $7
+ ; MMR3: sll16 $[[T1:[0-9]+]], $4, 1
+ ; MMR3: not16 $[[T2:[0-9]+]], $7
+ ; MMR3: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
+ ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]]
+ ; MMR3: srlv $[[T5:[0-9]+]], $4, $7
+ ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32
+ ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]]
+ ; MMR3: lui $[[T8:[0-9]+]], 0
+ ; MMR3: movn $2, $[[T8]], $[[T6]]
+
+ ; MMR6: srlv $[[T0:[0-9]+]], $5, $7
+ ; MMR6: not $[[T1:[0-9]+]], $7
+ ; MMR6: sll16 $[[T2:[0-9]+]], $4, 1
+ ; MMR6: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+ ; MMR6: or16 $[[T4:[0-9]+]], $[[T0]]
+ ; MMR6: andi16 $[[T5:[0-9]+]], $7, 32
+ ; MMR6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T5]]
+ ; MMR6: srlv $[[T7:[0-9]+]], $4, $7
+ ; MMR6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]]
+ ; MMR6: or $3, $[[T8]], $[[T6]]
+ ; MMR6: seleqz $2, $[[T7]], $[[T5]]
+
%r = lshr i64 %a, %b
ret i64 %r
}
@@ -182,6 +213,8 @@ entry:
; 64R6: jr $ra
; 64R6: seleqz $2, $[[T9]], $[[T7]]
+ ; MM: lw $25, %call16(__lshrti3)($2)
+
%r = lshr i128 %a, %b
ret i128 %r
}
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll?rev=267693&r1=267692&r2=267693&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll Wed Apr 27 06:02:23 2016
@@ -37,6 +37,10 @@
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
; RUN: -check-prefix=64R6 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MMR3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MMR6
define signext i1 @shl_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -61,6 +65,10 @@ entry:
; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]]
; R2-R6: seb $2, $[[T1]]
+ ; MM: andi16 $[[T0:[0-9]+]], $5, 255
+ ; MM: sllv $[[T1:[0-9]+]], $4, $[[T0]]
+ ; MM: seb $2, $[[T1]]
+
%r = shl i8 %a, %b
ret i8 %r
}
@@ -78,6 +86,10 @@ entry:
; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]]
; R2-R6: seh $2, $[[T1]]
+ ; MM: andi16 $[[T0:[0-9]+]], $5, 65535
+ ; MM: sllv $[[T1:[0-9]+]], $4, $[[T0]]
+ ; MM: seh $2, $[[T1]]
+
%r = shl i16 %a, %b
ret i16 %r
}
@@ -139,6 +151,29 @@ entry:
; GP64: dsllv $2, $4, $5
+ ; MMR3: sllv $[[T0:[0-9]+]], $4, $7
+ ; MMR3: srl16 $[[T1:[0-9]+]], $5, 1
+ ; MMR3: not16 $[[T2:[0-9]+]], $7
+ ; MMR3: srlv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
+ ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]]
+ ; MMR3: sllv $[[T5:[0-9]+]], $5, $7
+ ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32
+ ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]]
+ ; MMR3: lui $[[T8:[0-9]+]], 0
+ ; MMR3: movn $3, $[[T8]], $[[T6]]
+
+ ; MMR6: sllv $[[T0:[0-9]+]], $4, $7
+ ; MMR6: not $[[T1:[0-9]+]], $7
+ ; MMR6: srl16 $[[T2:[0-9]+]], $5, 1
+ ; MMR6: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+ ; MMR6: or16 $[[T4:[0-9]+]], $[[T0]]
+ ; MMR6: andi16 $[[T5:[0-9]+]], $7, 32
+ ; MMR6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T5]]
+ ; MMR6: sllv $[[T7:[0-9]+]], $5, $7
+ ; MMR6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]]
+ ; MMR6: or $2, $[[T8]], $[[T6]]
+ ; MMR6: seleqz $3, $[[T7]], $[[T5]]
+
%r = shl i64 %a, %b
ret i64 %r
}
@@ -194,6 +229,8 @@ entry:
; 64R6: jr $ra
; 64R6: seleqz $3, $[[T9]], $[[T7]]
+ ; MM: lw $25, %call16(__ashlti3)($2)
+
%r = shl i128 %a, %b
ret i128 %r
}
Modified: llvm/trunk/test/CodeGen/Mips/micromips-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-shift.ll?rev=267693&r1=267692&r2=267693&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-shift.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/micromips-shift.ll Wed Apr 27 06:02:23 2016
@@ -1,5 +1,7 @@
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+micromips \
+; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
@a = global i32 10, align 4
@b = global i32 0, align 4
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt?rev=267693&r1=267692&r2=267693&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt Wed Apr 27 06:02:23 2016
@@ -292,3 +292,8 @@
0x00 0x04 0x39 0x7c # CHECK: evp $4
0x03 0xe4 0x1f 0x3c # CHECK: jalrc.hb $4
0x00 0x85 0x1f 0x3c # CHECK: jalrc.hb $4, $5
+0x00 0x65 0x10 0x10 # CHECK: sllv $2, $3, $5
+0x00 0x83 0x38 0x80 # CHECK: sra $4, $3, 7
+0x00 0x65 0x10 0x90 # CHECK: srav $2, $3, $5
+0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7
+0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt?rev=267693&r1=267692&r2=267693&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt Wed Apr 27 06:02:23 2016
@@ -226,3 +226,9 @@
0x00 0x04 0x39 0x7c # CHECK: evp $4
0x03 0xe4 0x1f 0x3c # CHECK: jalrc.hb $4
0x00 0x85 0x1f 0x3c # CHECK: jalrc.hb $4, $5
+0x00 0x83 0x38 0x00 # CHECK: sll $4, $3, 7
+0x00 0x65 0x10 0x10 # CHECK: sllv $2, $3, $5
+0x00 0x83 0x38 0x80 # CHECK: sra $4, $3, 7
+0x00 0x65 0x10 0x90 # CHECK: srav $2, $3, $5
+0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7
+0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5
Modified: llvm/trunk/test/MC/Mips/micromips-shift-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-shift-instructions.s?rev=267693&r1=267692&r2=267693&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-shift-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-shift-instructions.s Wed Apr 27 06:02:23 2016
@@ -15,6 +15,15 @@
# CHECK-EL: srlv $2, $3, $5 # encoding: [0x65,0x00,0x50,0x10]
# CHECK-EL: rotr $9, $6, 7 # encoding: [0x26,0x01,0xc0,0x38]
# CHECK-EL: rotrv $9, $6, $7 # encoding: [0xc7,0x00,0xd0,0x48]
+# CHECK-EL: sllv $2, $3, $5 # encoding: [0x65,0x00,0x10,0x10]
+# CHECK-EL: srav $2, $3, $5 # encoding: [0x65,0x00,0x90,0x10]
+# CHECK-EL: srlv $2, $3, $5 # encoding: [0x65,0x00,0x50,0x10]
+# CHECK-EL: sllv $2, $2, $3 # encoding: [0x43,0x00,0x10,0x10]
+# CHECK-EL: srav $2, $2, $3 # encoding: [0x43,0x00,0x90,0x10]
+# CHECK-EL: srlv $2, $2, $3 # encoding: [0x43,0x00,0x50,0x10]
+# CHECK-EL: sll $3, $3, 7 # encoding: [0x63,0x00,0x00,0x38]
+# CHECK-EL: sra $3, $3, 7 # encoding: [0x63,0x00,0x80,0x38]
+# CHECK-EL: srl $3, $3, 7 # encoding: [0x63,0x00,0x40,0x38]
#------------------------------------------------------------------------------
# Big endian
#------------------------------------------------------------------------------
@@ -26,6 +35,15 @@
# CHECK-EB: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50]
# CHECK-EB: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
# CHECK-EB: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
+# CHECK-EB: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
+# CHECK-EB: srav $2, $3, $5 # encoding: [0x00,0x65,0x10,0x90]
+# CHECK-EB: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50]
+# CHECK-EB: sllv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x10]
+# CHECK-EB: srav $2, $2, $3 # encoding: [0x00,0x43,0x10,0x90]
+# CHECK-EB: srlv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x50]
+# CHECK-EB: sll $3, $3, 7 # encoding: [0x00,0x63,0x38,0x00]
+# CHECK-EB: sra $3, $3, 7 # encoding: [0x00,0x63,0x38,0x80]
+# CHECK-EB: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40]
sll $4, $3, 7
sllv $2, $3, $5
sra $4, $3, 7
@@ -34,3 +52,12 @@
srlv $2, $3, $5
rotr $9, $6, 7
rotrv $9, $6, $7
+ sll $2, $3, $5
+ sra $2, $3, $5
+ srl $2, $3, $5
+ sll $2, $3
+ sra $2, $3
+ srl $2, $3
+ sll $3, 7
+ sra $3, 7
+ srl $3, 7
Modified: llvm/trunk/test/MC/Mips/micromips/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips/invalid.s?rev=267693&r1=267692&r2=267693&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips/invalid.s Wed Apr 27 06:02:23 2016
@@ -52,3 +52,8 @@
sync 32 # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
swe $2, -513($gp) # CHECK: :[[@LINE]]:11: error: expected memory with $gp and 9-bit signed offset
swe $2, 512($gp) # CHECK: :[[@LINE]]:11: error: expected memory with $gp and 9-bit signed offset
+ sll $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+ sll $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+ sra $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+ sra $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+ srl $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
Modified: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/invalid.s?rev=267693&r1=267692&r2=267693&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s Wed Apr 27 06:02:23 2016
@@ -139,3 +139,15 @@
evp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
jalrc.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
jalrc.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
+ sll $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+ sll $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+ sra $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+ sra $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+ srl $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+ srl $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+ sll $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+ sll $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+ sra $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+ sra $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+ srl $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+ srl $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=267693&r1=267692&r2=267693&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Wed Apr 27 06:02:23 2016
@@ -291,3 +291,17 @@
evp $4 # CHECK: evp $4 # encoding: [0x00,0x04,0x39,0x7c]
jalrc.hb $4 # CHECK: jalrc.hb $4 # encoding: [0x03,0xe4,0x1f,0x3c]
jalrc.hb $4, $5 # CHECK: jalrc.hb $4, $5 # encoding: [0x00,0x85,0x1f,0x3c]
+ sllv $2, $3, $5 # CHECK: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
+ sra $4, $3, 7 # CHECK: sra $4, $3, 7 # encoding: [0x00,0x83,0x38,0x80]
+ srav $2, $3, $5 # CHECK: srav $2, $3, $5 # encoding: [0x00,0x65,0x10,0x90]
+ srl $4, $3, 7 # CHECK: srl $4, $3, 7 # encoding: [0x00,0x83,0x38,0x40]
+ srlv $2, $3, $5 # CHECK: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50]
+ sll $2, $3, $5 # CHECK: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
+ sra $2, $3, $5 # CHECK: srav $2, $3, $5 # encoding: [0x00,0x65,0x10,0x90]
+ srl $2, $3, $5 # CHECK: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50]
+ sll $2, $3 # CHECK: sllv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x10]
+ sra $2, $3 # CHECK: srav $2, $2, $3 # encoding: [0x00,0x43,0x10,0x90]
+ srl $2, $3 # CHECK: srlv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x50]
+ sll $3, 7 # CHECK: sll $3, $3, 7 # encoding: [0x00,0x63,0x38,0x00]
+ sra $3, 7 # CHECK: sra $3, $3, 7 # encoding: [0x00,0x63,0x38,0x80]
+ srl $3, 7 # CHECK: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40]
Modified: llvm/trunk/test/MC/Mips/micromips64r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/invalid.s?rev=267693&r1=267692&r2=267693&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/invalid.s Wed Apr 27 06:02:23 2016
@@ -164,3 +164,15 @@
evp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
jalrc.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
jalrc.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
+ sll $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+ sll $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+ sra $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+ sra $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+ srl $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+ srl $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+ sll $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+ sll $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+ sra $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+ sra $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+ srl $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+ srl $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
Modified: llvm/trunk/test/MC/Mips/micromips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/valid.s?rev=267693&r1=267692&r2=267693&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/valid.s Wed Apr 27 06:02:23 2016
@@ -209,5 +209,19 @@ a:
evp $4 # CHECK: evp $4 # encoding: [0x00,0x04,0x39,0x7c]
jalrc.hb $4 # CHECK: jalrc.hb $4 # encoding: [0x03,0xe4,0x1f,0x3c]
jalrc.hb $4, $5 # CHECK: jalrc.hb $4, $5 # encoding: [0x00,0x85,0x1f,0x3c]
+ sllv $2, $3, $5 # CHECK: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
+ sra $4, $3, 7 # CHECK: sra $4, $3, 7 # encoding: [0x00,0x83,0x38,0x80]
+ srav $2, $3, $5 # CHECK: srav $2, $3, $5 # encoding: [0x00,0x65,0x10,0x90]
+ srl $4, $3, 7 # CHECK: srl $4, $3, 7 # encoding: [0x00,0x83,0x38,0x40]
+ srlv $2, $3, $5 # CHECK: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50]
+ sll $2, $3, $5 # CHECK: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
+ sra $2, $3, $5 # CHECK: srav $2, $3, $5 # encoding: [0x00,0x65,0x10,0x90]
+ srl $2, $3, $5 # CHECK: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50]
+ sll $2, $3 # CHECK: sllv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x10]
+ sra $2, $3 # CHECK: srav $2, $2, $3 # encoding: [0x00,0x43,0x10,0x90]
+ srl $2, $3 # CHECK: srlv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x50]
+ sll $3, 7 # CHECK: sll $3, $3, 7 # encoding: [0x00,0x63,0x38,0x00]
+ sra $3, 7 # CHECK: sra $3, $3, 7 # encoding: [0x00,0x63,0x38,0x80]
+ srl $3, 7 # CHECK: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40]
1:
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