[PATCH] D19450: Add optimization bisect opt-in calls for AMDGPU passes

Andy Kaylor via llvm-commits llvm-commits at lists.llvm.org
Fri Apr 22 18:19:44 PDT 2016


andrew.w.kaylor created this revision.
andrew.w.kaylor added a reviewer: tstellarAMD.
andrew.w.kaylor added a subscriber: llvm-commits.
andrew.w.kaylor set the repository for this revision to rL LLVM.
Herald added a subscriber: arsenm.

This patch adds calls to AMDGPU-specific passes that can be safely skipped to opt-in to the optimization bisect mechanism.

The following passes are not calling the opt-in function:

AMDGPUAlwaysInline
AMDGPUAnnotateKernelFeatures
AMDGPUCFGStructurizer
AMDGPUOpenCLImageTypeLoweringPass
R600ControlFlowFinalizer
R600EmitClauseMarkers
R600ExpandSpecialInstrsPass
R600Packetizer
R600TextureIntrinsicsReplacer
SIAnnotateControlFlow
SIFixControlFlowLiveIntervals
SIFixSGPRCopies
SIInsertNops
SIInsertWaits
SILowerControlFlow
SILowerI1Copies
SITypeRewriter
SIWholeQuadMode

Note that the call to skipFunction() will also check for the "optnone" function attribute, so this can theoretically result in passes being skipped even when optimization bisect is not being done. However, I believe that any pass that can be safely skipped should be skipped for functions with the optnone attribute.  Where the OptNone function attribute was being checked, it is now being checked within the call to skipFunction().

Repository:
  rL LLVM

http://reviews.llvm.org/D19450

Files:
  lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
  lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
  lib/Target/AMDGPU/R600ClauseMergePass.cpp
  lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
  lib/Target/AMDGPU/SIFoldOperands.cpp
  lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  lib/Target/AMDGPU/SIShrinkInstructions.cpp

Index: lib/Target/AMDGPU/R600ClauseMergePass.cpp
===================================================================
--- lib/Target/AMDGPU/R600ClauseMergePass.cpp
+++ lib/Target/AMDGPU/R600ClauseMergePass.cpp
@@ -168,6 +168,9 @@
 }
 
 bool R600ClauseMergePass::runOnMachineFunction(MachineFunction &MF) {
+  if (skipFunction(*MF.getFunction()))
+    return false;
+
   TII = static_cast<const R600InstrInfo *>(MF.getSubtarget().getInstrInfo());
   for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
                                                   BB != BB_E; ++BB) {
Index: lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
===================================================================
--- lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -423,6 +423,9 @@
 }
 
 bool SILoadStoreOptimizer::runOnMachineFunction(MachineFunction &MF) {
+  if (skipFunction(*MF.getFunction()))
+    return false;
+
   const TargetSubtargetInfo &STM = MF.getSubtarget();
   TRI = static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
   TII = static_cast<const SIInstrInfo *>(STM.getInstrInfo());
Index: lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
+++ lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
@@ -88,6 +88,9 @@
 }
 
 bool AMDGPUAnnotateUniformValues::runOnFunction(Function &F) {
+  if (skipFunction(F))
+    return false;
+
   DA = &getAnalysis<DivergenceAnalysis>();
   visit(F);
 
Index: lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
===================================================================
--- lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
+++ lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
@@ -314,6 +314,9 @@
 }
 
 bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) {
+  if (skipFunction(*Fn.getFunction()))
+    return false;
+
   TII = static_cast<const R600InstrInfo *>(Fn.getSubtarget().getInstrInfo());
   MRI = &(Fn.getRegInfo());
   for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
Index: lib/Target/AMDGPU/SIFoldOperands.cpp
===================================================================
--- lib/Target/AMDGPU/SIFoldOperands.cpp
+++ lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -295,6 +295,9 @@
 }
 
 bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
+  if (skipFunction(*MF.getFunction()))
+    return false;
+
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const SIInstrInfo *TII =
       static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
Index: lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+++ lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
@@ -97,7 +97,7 @@
 }
 
 bool AMDGPUPromoteAlloca::runOnFunction(Function &F) {
-  if (!TM || F.hasFnAttribute(Attribute::OptimizeNone))
+  if (!TM || skipFunction(F))
     return false;
 
   FunctionType *FTy = F.getFunctionType();
Index: lib/Target/AMDGPU/SIShrinkInstructions.cpp
===================================================================
--- lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -203,6 +203,9 @@
 }
 
 bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
+  if (skipFunction(*MF.getFunction()))
+    return false;
+
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const SIInstrInfo *TII =
       static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());


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