[llvm] r267244 - AMDGPU: sext_inreg (srl x, K), vt -> bfe x, K, vt.Size
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 22 15:59:16 PDT 2016
Author: arsenm
Date: Fri Apr 22 17:59:16 2016
New Revision: 267244
URL: http://llvm.org/viewvc/llvm-project?rev=267244&view=rev
Log:
AMDGPU: sext_inreg (srl x, K), vt -> bfe x, K, vt.Size
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
llvm/trunk/test/CodeGen/AMDGPU/sign_extend.ll
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp?rev=267244&r1=267243&r2=267244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp Fri Apr 22 17:59:16 2016
@@ -531,6 +531,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNod
case ISD::AND:
case ISD::SRL:
case ISD::SRA:
+ case ISD::SIGN_EXTEND_INREG:
if (N->getValueType(0) != MVT::i32 ||
Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
break;
@@ -1478,6 +1479,21 @@ SDNode *AMDGPUDAGToDAGISel::SelectS_BFE(
if (N->getOperand(0).getOpcode() == ISD::SHL)
return SelectS_BFEFromShifts(N);
break;
+
+ case ISD::SIGN_EXTEND_INREG: {
+ // sext_inreg (srl x, 16), i8 -> bfe_i32 x, 16, 8
+ SDValue Src = N->getOperand(0);
+ if (Src.getOpcode() != ISD::SRL)
+ break;
+
+ const ConstantSDNode *Amt = dyn_cast<ConstantSDNode>(Src.getOperand(1));
+ if (!Amt)
+ break;
+
+ unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
+ return getS_BFE(AMDGPU::S_BFE_I32, SDLoc(N), Src.getOperand(0),
+ Amt->getZExtValue(), Width);
+ }
}
return SelectCode(N);
Modified: llvm/trunk/test/CodeGen/AMDGPU/sign_extend.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/sign_extend.ll?rev=267244&r1=267243&r2=267244&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/sign_extend.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/sign_extend.ll Fri Apr 22 17:59:16 2016
@@ -1,9 +1,9 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
-; SI-LABEL: {{^}}s_sext_i1_to_i32:
-; SI: v_cndmask_b32_e64
-; SI: s_endpgm
+; GCN-LABEL: {{^}}s_sext_i1_to_i32:
+; GCN: v_cndmask_b32_e64
+; GCN: s_endpgm
define void @s_sext_i1_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%cmp = icmp eq i32 %a, %b
%sext = sext i1 %cmp to i32
@@ -11,9 +11,9 @@ define void @s_sext_i1_to_i32(i32 addrsp
ret void
}
-; SI-LABEL: {{^}}test_s_sext_i32_to_i64:
-; SI: s_ashr_i32
-; SI: s_endpg
+; GCN-LABEL: {{^}}test_s_sext_i32_to_i64:
+; GCN: s_ashr_i32
+; GCN: s_endpg
define void @test_s_sext_i32_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) nounwind {
entry:
%mul = mul i32 %a, %b
@@ -23,11 +23,11 @@ entry:
ret void
}
-; SI-LABEL: {{^}}s_sext_i1_to_i64:
-; SI: v_cndmask_b32_e64 v[[LOREG:[0-9]+]], 0, -1, vcc
-; SI: v_mov_b32_e32 v[[HIREG:[0-9]+]], v[[LOREG]]
-; SI: buffer_store_dwordx2 v{{\[}}[[LOREG]]:[[HIREG]]{{\]}}
-; SI: s_endpgm
+; GCN-LABEL: {{^}}s_sext_i1_to_i64:
+; GCN: v_cndmask_b32_e64 v[[LOREG:[0-9]+]], 0, -1, vcc
+; GCN: v_mov_b32_e32 v[[HIREG:[0-9]+]], v[[LOREG]]
+; GCN: buffer_store_dwordx2 v{{\[}}[[LOREG]]:[[HIREG]]{{\]}}
+; GCN: s_endpgm
define void @s_sext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%cmp = icmp eq i32 %a, %b
%sext = sext i1 %cmp to i64
@@ -35,18 +35,18 @@ define void @s_sext_i1_to_i64(i64 addrsp
ret void
}
-; SI-LABEL: {{^}}s_sext_i32_to_i64:
-; SI: s_ashr_i32
-; SI: s_endpgm
+; GCN-LABEL: {{^}}s_sext_i32_to_i64:
+; GCN: s_ashr_i32
+; GCN: s_endpgm
define void @s_sext_i32_to_i64(i64 addrspace(1)* %out, i32 %a) nounwind {
%sext = sext i32 %a to i64
store i64 %sext, i64 addrspace(1)* %out, align 8
ret void
}
-; SI-LABEL: {{^}}v_sext_i32_to_i64:
-; SI: v_ashr
-; SI: s_endpgm
+; GCN-LABEL: {{^}}v_sext_i32_to_i64:
+; GCN: v_ashr
+; GCN: s_endpgm
define void @v_sext_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
%val = load i32, i32 addrspace(1)* %in, align 4
%sext = sext i32 %val to i64
@@ -54,10 +54,112 @@ define void @v_sext_i32_to_i64(i64 addrs
ret void
}
-; SI-LABEL: {{^}}s_sext_i16_to_i64:
-; SI: s_endpgm
+; GCN-LABEL: {{^}}s_sext_i16_to_i64:
+; GCN: s_endpgm
define void @s_sext_i16_to_i64(i64 addrspace(1)* %out, i16 %a) nounwind {
%sext = sext i16 %a to i64
store i64 %sext, i64 addrspace(1)* %out, align 8
ret void
}
+
+; GCN-LABEL: {{^}}s_sext_v4i8_to_v4i32:
+; GCN: s_load_dword [[VAL:s[0-9]+]]
+; GCN-DAG: s_sext_i32_i8 [[EXT0:s[0-9]+]], [[VAL]]
+; GCN-DAG: s_bfe_i32 [[EXT1:s[0-9]+]], [[VAL]], 0x80008
+; GCN-DAG: s_bfe_i32 [[EXT2:s[0-9]+]], [[VAL]], 0x80010
+; GCN-DAG: s_ashr_i32 [[EXT3:s[0-9]+]], [[VAL]], 24
+
+; GCN-DAG: v_mov_b32_e32 [[VEXT0:v[0-9]+]], [[EXT0]]
+; GCN-DAG: v_mov_b32_e32 [[VEXT1:v[0-9]+]], [[EXT1]]
+; GCN-DAG: v_mov_b32_e32 [[VEXT2:v[0-9]+]], [[EXT2]]
+; GCN-DAG: v_mov_b32_e32 [[VEXT3:v[0-9]+]], [[EXT3]]
+
+; GCN-DAG: buffer_store_dword [[VEXT0]]
+; GCN-DAG: buffer_store_dword [[VEXT1]]
+; GCN-DAG: buffer_store_dword [[VEXT2]]
+; GCN-DAG: buffer_store_dword [[VEXT3]]
+
+; GCN: s_endpgm
+define void @s_sext_v4i8_to_v4i32(i32 addrspace(1)* %out, i32 %a) nounwind {
+ %cast = bitcast i32 %a to <4 x i8>
+ %ext = sext <4 x i8> %cast to <4 x i32>
+ %elt0 = extractelement <4 x i32> %ext, i32 0
+ %elt1 = extractelement <4 x i32> %ext, i32 1
+ %elt2 = extractelement <4 x i32> %ext, i32 2
+ %elt3 = extractelement <4 x i32> %ext, i32 3
+ store volatile i32 %elt0, i32 addrspace(1)* %out
+ store volatile i32 %elt1, i32 addrspace(1)* %out
+ store volatile i32 %elt2, i32 addrspace(1)* %out
+ store volatile i32 %elt3, i32 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_sext_v4i8_to_v4i32:
+; GCN: buffer_load_dword [[VAL:v[0-9]+]]
+; GCN-DAG: v_bfe_i32 [[EXT0:v[0-9]+]], [[VAL]], 0, 8
+; GCN-DAG: v_bfe_i32 [[EXT1:v[0-9]+]], [[VAL]], 8, 8
+; GCN-DAG: v_bfe_i32 [[EXT2:v[0-9]+]], [[VAL]], 16, 8
+; GCN-DAG: v_ashrrev_i32_e32 [[EXT3:v[0-9]+]], 24, [[VAL]]
+
+; GCN: buffer_store_dword [[EXT0]]
+; GCN: buffer_store_dword [[EXT1]]
+; GCN: buffer_store_dword [[EXT2]]
+; GCN: buffer_store_dword [[EXT3]]
+define void @v_sext_v4i8_to_v4i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
+ %a = load i32, i32 addrspace(1)* %in
+ %cast = bitcast i32 %a to <4 x i8>
+ %ext = sext <4 x i8> %cast to <4 x i32>
+ %elt0 = extractelement <4 x i32> %ext, i32 0
+ %elt1 = extractelement <4 x i32> %ext, i32 1
+ %elt2 = extractelement <4 x i32> %ext, i32 2
+ %elt3 = extractelement <4 x i32> %ext, i32 3
+ store volatile i32 %elt0, i32 addrspace(1)* %out
+ store volatile i32 %elt1, i32 addrspace(1)* %out
+ store volatile i32 %elt2, i32 addrspace(1)* %out
+ store volatile i32 %elt3, i32 addrspace(1)* %out
+ ret void
+}
+
+; FIXME: s_bfe_i64
+; GCN-LABEL: {{^}}s_sext_v4i16_to_v4i32:
+; GCN-DAG: s_ashr_i64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 48
+; GCN-DAG: s_ashr_i32 s{{[0-9]+}}, s{{[0-9]+}}, 16
+; GCN-DAG: s_sext_i32_i16
+; GCN-DAG: s_sext_i32_i16
+; GCN: s_endpgm
+define void @s_sext_v4i16_to_v4i32(i32 addrspace(1)* %out, i64 %a) nounwind {
+ %cast = bitcast i64 %a to <4 x i16>
+ %ext = sext <4 x i16> %cast to <4 x i32>
+ %elt0 = extractelement <4 x i32> %ext, i32 0
+ %elt1 = extractelement <4 x i32> %ext, i32 1
+ %elt2 = extractelement <4 x i32> %ext, i32 2
+ %elt3 = extractelement <4 x i32> %ext, i32 3
+ store volatile i32 %elt0, i32 addrspace(1)* %out
+ store volatile i32 %elt1, i32 addrspace(1)* %out
+ store volatile i32 %elt2, i32 addrspace(1)* %out
+ store volatile i32 %elt3, i32 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_sext_v4i16_to_v4i32:
+; SI-DAG: v_ashr_i64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, 48
+; VI-DAG: v_ashrrev_i64 v{{\[[0-9]+:[0-9]+\]}}, 48, v{{\[[0-9]+:[0-9]+\]}}
+; GCN-DAG: v_ashrrev_i32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
+; GCN-DAG: v_ashrrev_i32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
+; GCN-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16
+; GCN-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16
+; GCN: s_endpgm
+define void @v_sext_v4i16_to_v4i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
+ %a = load i64, i64 addrspace(1)* %in
+ %cast = bitcast i64 %a to <4 x i16>
+ %ext = sext <4 x i16> %cast to <4 x i32>
+ %elt0 = extractelement <4 x i32> %ext, i32 0
+ %elt1 = extractelement <4 x i32> %ext, i32 1
+ %elt2 = extractelement <4 x i32> %ext, i32 2
+ %elt3 = extractelement <4 x i32> %ext, i32 3
+ store volatile i32 %elt0, i32 addrspace(1)* %out
+ store volatile i32 %elt1, i32 addrspace(1)* %out
+ store volatile i32 %elt2, i32 addrspace(1)* %out
+ store volatile i32 %elt3, i32 addrspace(1)* %out
+ ret void
+}
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