[llvm] r267038 - [Hexagon] Properly recognize register alt names
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 21 12:49:53 PDT 2016
Author: kparzysz
Date: Thu Apr 21 14:49:53 2016
New Revision: 267038
URL: http://llvm.org/viewvc/llvm-project?rev=267038&view=rev
Log:
[Hexagon] Properly recognize register alt names
Added:
llvm/trunk/test/MC/Hexagon/register-alt-names.s
Modified:
llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
llvm/trunk/lib/Target/Hexagon/Hexagon.td
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td
Modified: llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=267038&r1=267037&r2=267038&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp Thu Apr 21 14:49:53 2016
@@ -124,6 +124,8 @@ class HexagonAsmParser : public MCTarget
getAssembler()->setELFHeaderEFlags(flags);
}
+ unsigned matchRegister(StringRef Name);
+
/// @name Auto-generated Match Functions
/// {
@@ -616,9 +618,6 @@ void HexagonOperand::print(raw_ostream &
}
}
-/// @name Auto-generated Match Functions
-static unsigned MatchRegisterName(StringRef Name);
-
bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) {
DEBUG(dbgs() << "Bundle:");
DEBUG(MCB.dump_pretty(dbgs()));
@@ -1182,7 +1181,7 @@ bool HexagonAsmParser::isLabel(AsmToken
return false;
if (!Token.is(AsmToken::TokenKind::Identifier))
return true;
- if (!MatchRegisterName(String.lower()))
+ if (!matchRegister(String.lower()))
return true;
(void)Second;
assert(Second.is(AsmToken::Colon));
@@ -1193,7 +1192,7 @@ bool HexagonAsmParser::isLabel(AsmToken
Collapsed.end());
StringRef Whole = Collapsed;
std::pair<StringRef, StringRef> DotSplit = Whole.split('.');
- if (!MatchRegisterName(DotSplit.first.lower()))
+ if (!matchRegister(DotSplit.first.lower()))
return true;
return false;
}
@@ -1238,7 +1237,7 @@ bool HexagonAsmParser::ParseRegister(uns
Collapsed.end());
StringRef FullString = Collapsed;
std::pair<StringRef, StringRef> DotSplit = FullString.split('.');
- unsigned DotReg = MatchRegisterName(DotSplit.first.lower());
+ unsigned DotReg = matchRegister(DotSplit.first.lower());
if (DotReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
if (DotSplit.second.empty()) {
RegNo = DotReg;
@@ -1258,7 +1257,7 @@ bool HexagonAsmParser::ParseRegister(uns
}
}
std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':');
- unsigned ColonReg = MatchRegisterName(ColonSplit.first.lower());
+ unsigned ColonReg = matchRegister(ColonSplit.first.lower());
if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
Lexer.UnLex(Lookahead.back());
Lookahead.pop_back();
@@ -1617,11 +1616,11 @@ int HexagonAsmParser::processInstruction
unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
std::string R1 = r + llvm::utostr(RegPairNum + 1);
StringRef Reg1(R1);
- MO.setReg(MatchRegisterName(Reg1));
+ MO.setReg(matchRegister(Reg1));
// Add a new operand for the second register in the pair.
std::string R2 = r + llvm::utostr(RegPairNum);
StringRef Reg2(R2);
- Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));
+ Inst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
Inst.setOpcode(Hexagon::A2_combinew);
break;
}
@@ -1632,11 +1631,11 @@ int HexagonAsmParser::processInstruction
unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
std::string R1 = r + llvm::utostr(RegPairNum + 1);
StringRef Reg1(R1);
- MO.setReg(MatchRegisterName(Reg1));
+ MO.setReg(matchRegister(Reg1));
// Add a new operand for the second register in the pair.
std::string R2 = r + llvm::utostr(RegPairNum);
StringRef Reg2(R2);
- Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));
+ Inst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
? Hexagon::C2_ccombinewt
: Hexagon::C2_ccombinewf);
@@ -1648,11 +1647,11 @@ int HexagonAsmParser::processInstruction
unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
std::string R1 = r + llvm::utostr(RegPairNum + 1);
StringRef Reg1(R1);
- MO.setReg(MatchRegisterName(Reg1));
+ MO.setReg(matchRegister(Reg1));
// Add a new operand for the second register in the pair.
std::string R2 = r + llvm::utostr(RegPairNum);
StringRef Reg2(R2);
- Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));
+ Inst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew)
? Hexagon::C2_ccombinewnewt
: Hexagon::C2_ccombinewnewf);
@@ -1977,14 +1976,14 @@ int HexagonAsmParser::processInstruction
unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());
std::string R1 = r + llvm::utostr(RegPairNum + 1);
StringRef Reg1(R1);
- Rss.setReg(MatchRegisterName(Reg1));
+ Rss.setReg(matchRegister(Reg1));
// Add a new operand for the second register in the pair.
std::string R2 = r + llvm::utostr(RegPairNum);
StringRef Reg2(R2);
TmpInst.setOpcode(Hexagon::A2_combinew);
TmpInst.addOperand(Rdd);
TmpInst.addOperand(Rss);
- TmpInst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));
+ TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
Inst = TmpInst;
} else {
Imm.setExpr(HexagonMCExpr::create(
@@ -2004,13 +2003,13 @@ int HexagonAsmParser::processInstruction
std::string Name =
r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
StringRef RegPair = Name;
- Rs.setReg(MatchRegisterName(RegPair));
+ Rs.setReg(matchRegister(RegPair));
} else { // raw:lo
Inst.setOpcode(Hexagon::A4_boundscheck_lo);
std::string Name =
r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
StringRef RegPair = Name;
- Rs.setReg(MatchRegisterName(RegPair));
+ Rs.setReg(matchRegister(RegPair));
}
break;
}
@@ -2023,13 +2022,13 @@ int HexagonAsmParser::processInstruction
std::string Name =
r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
StringRef RegPair = Name;
- Rs.setReg(MatchRegisterName(RegPair));
+ Rs.setReg(matchRegister(RegPair));
} else { // Even mapped raw:lo
Inst.setOpcode(Hexagon::A2_addspl);
std::string Name =
r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
StringRef RegPair = Name;
- Rs.setReg(MatchRegisterName(RegPair));
+ Rs.setReg(matchRegister(RegPair));
}
break;
}
@@ -2042,13 +2041,13 @@ int HexagonAsmParser::processInstruction
std::string Name =
r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
StringRef RegPair = Name;
- Rt.setReg(MatchRegisterName(RegPair));
+ Rt.setReg(matchRegister(RegPair));
} else { // Even mapped sat:raw:lo
Inst.setOpcode(Hexagon::M2_vrcmpys_s1_l);
std::string Name =
r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
StringRef RegPair = Name;
- Rt.setReg(MatchRegisterName(RegPair));
+ Rt.setReg(matchRegister(RegPair));
}
break;
}
@@ -2064,13 +2063,13 @@ int HexagonAsmParser::processInstruction
std::string Name =
r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
StringRef RegPair = Name;
- Rt.setReg(MatchRegisterName(RegPair));
+ Rt.setReg(matchRegister(RegPair));
} else { // Even mapped sat:raw:lo
TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
std::string Name =
r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
StringRef RegPair = Name;
- Rt.setReg(MatchRegisterName(RegPair));
+ Rt.setReg(matchRegister(RegPair));
}
// Registers are in different positions
TmpInst.addOperand(Rxx);
@@ -2089,13 +2088,13 @@ int HexagonAsmParser::processInstruction
std::string Name =
r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
StringRef RegPair = Name;
- Rt.setReg(MatchRegisterName(RegPair));
+ Rt.setReg(matchRegister(RegPair));
} else { // Even mapped rnd:sat:raw:lo
Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
std::string Name =
r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
StringRef RegPair = Name;
- Rt.setReg(MatchRegisterName(RegPair));
+ Rt.setReg(matchRegister(RegPair));
}
break;
}
@@ -2131,14 +2130,14 @@ int HexagonAsmParser::processInstruction
unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());
std::string R1 = r + llvm::utostr(RegPairNum + 1);
StringRef Reg1(R1);
- Rss.setReg(MatchRegisterName(Reg1));
+ Rss.setReg(matchRegister(Reg1));
// Add a new operand for the second register in the pair.
std::string R2 = r + llvm::utostr(RegPairNum);
StringRef Reg2(R2);
TmpInst.setOpcode(Hexagon::A2_combinew);
TmpInst.addOperand(Rdd);
TmpInst.addOperand(Rss);
- TmpInst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));
+ TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
Inst = TmpInst;
} else {
Imm.setExpr(HexagonMCExpr::create(
@@ -2166,3 +2165,10 @@ int HexagonAsmParser::processInstruction
return Match_Success;
}
+
+
+unsigned HexagonAsmParser::matchRegister(StringRef Name) {
+ if (unsigned Reg = MatchRegisterName(Name))
+ return Reg;
+ return MatchRegisterAltName(Name);
+}
Modified: llvm/trunk/lib/Target/Hexagon/Hexagon.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.td?rev=267038&r1=267037&r2=267038&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/Hexagon.td (original)
+++ llvm/trunk/lib/Target/Hexagon/Hexagon.td Thu Apr 21 14:49:53 2016
@@ -252,6 +252,7 @@ def : Proc<"hexagonv60", HexagonModelV60
//===----------------------------------------------------------------------===//
def HexagonAsmParser : AsmParser {
+ let ShouldEmitMatchRegisterAltName = 1;
bit HasMnemonicFirst = 0;
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td?rev=267038&r1=267037&r2=267038&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td Thu Apr 21 14:49:53 2016
@@ -13,8 +13,8 @@
let Namespace = "Hexagon" in {
- class HexagonReg<bits<5> num, string n, list<string> alt = [],
- list<Register> alias = []> : Register<n> {
+ class HexagonReg<bits<5> num, string n, list<string> alt = [],
+ list<Register> alias = []> : Register<n, alt> {
field bits<5> Num;
let Aliases = alias;
let HWEncoding{4-0} = num;
@@ -31,7 +31,8 @@ let Namespace = "Hexagon" in {
// Registers are identified with 5-bit ID numbers.
// Ri - 32-bit integer registers.
- class Ri<bits<5> num, string n, list<string> alt = []> : HexagonReg<num, n, alt> {
+ class Ri<bits<5> num, string n, list<string> alt = []> :
+ HexagonReg<num, n, alt> {
let Num = num;
}
@@ -42,8 +43,9 @@ let Namespace = "Hexagon" in {
// Rd - 64-bit registers.
- class Rd<bits<5> num, string n, list<Register> subregs> :
- HexagonDoubleReg<num, n, subregs> {
+ class Rd<bits<5> num, string n, list<Register> subregs,
+ list<string> alt = []> :
+ HexagonDoubleReg<num, n, subregs, alt> {
let Num = num;
let SubRegs = subregs;
}
@@ -94,11 +96,11 @@ let Namespace = "Hexagon" in {
// Aliases of the R* registers used to hold 64-bit int values (doubles).
let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
- def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
- def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
- def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
- def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
- def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
+ def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
+ def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
+ def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
+ def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
+ def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>;
def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>;
@@ -109,7 +111,7 @@ let Namespace = "Hexagon" in {
def D12 : Rd<24, "r25:24", [R24, R25]>, DwarfRegNum<[56]>;
def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>;
def D14 : Rd<28, "r29:28", [R28, R29]>, DwarfRegNum<[60]>;
- def D15 : Rd<30, "r31:30", [R30, R31]>, DwarfRegNum<[62]>;
+ def D15 : Rd<30, "r31:30", [R30, R31], ["lr:fp"]>, DwarfRegNum<[62]>;
}
// Predicate registers.
Added: llvm/trunk/test/MC/Hexagon/register-alt-names.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/register-alt-names.s?rev=267038&view=auto
==============================================================================
--- llvm/trunk/test/MC/Hexagon/register-alt-names.s (added)
+++ llvm/trunk/test/MC/Hexagon/register-alt-names.s Thu Apr 21 14:49:53 2016
@@ -0,0 +1,14 @@
+# RUN: llvm-mc -arch=hexagon < %s | FileCheck %s
+
+# CHECK: r0 = r31
+r0 = lr
+
+# CHECK: r1 = r30
+r1 = fp
+
+# CHECK: r2 = r29
+r2 = sp
+
+# CHECK: r1:0 = combine(r31, r30)
+r1:0 = lr:fp
+
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