[PATCH] D15009: [mips][microMIPS] Implement ldpc instruction

[Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL266990: [mips][microMIPS] Implement ldpc instruction (authored by zjovanovic).

Changed prior to commit:
  http://reviews.llvm.org/D15009?vs=41246&id=54502#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D15009

Files:
  llvm/trunk/lib/Target/Mips/MicroMips64r6InstrFormats.td
  llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td
  llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td
  llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt
  llvm/trunk/test/MC/Mips/micromips64r6/valid.s

Index: llvm/trunk/lib/Target/Mips/MicroMips64r6InstrFormats.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips64r6InstrFormats.td
+++ llvm/trunk/lib/Target/Mips/MicroMips64r6InstrFormats.td
@@ -130,3 +130,15 @@
   let Inst{20-16} = rs;
   let Inst{15-0}  = imm16;
 }
+
+class PCREL18_FM_MMR6<bits<3> funct> : MipsR6Inst {
+  bits<5> rt;
+  bits<18> imm;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b011110;
+  let Inst{25-21} = rt;
+  let Inst{20-18} = funct;
+  let Inst{17-0} = imm;
+}
Index: llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td
+++ llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td
@@ -40,6 +40,7 @@
 class DADD_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dadd", 0b100010000>;
 class DADDIU_MM64R6_ENC : DADDIU_FM_MMR6<"daddiu">;
 class DADDU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"daddu", 0b101010000>;
+class LDPC_MMR646_ENC : PCREL18_FM_MMR6<0b110>;
 
 //===----------------------------------------------------------------------===//
 //
@@ -123,6 +124,8 @@
                            IsAsCheapAsAMove;
 class DADDU_MM64R6_DESC : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>;
 
+class LDPC_MM64R6_DESC : PCREL_MMR6_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
@@ -173,6 +176,8 @@
                      ISA_MICROMIPS64R6;
   def DADDU_MM64R6: StdMMR6Rel, DADDU_MM64R6_DESC, DADDU_MM64R6_ENC,
                     ISA_MICROMIPS64R6;
+  def LDPC_MM64R6 :  R6MMR6Rel, LDPC_MMR646_ENC, LDPC_MM64R6_DESC,
+                     ISA_MICROMIPS64R6;
 }
 
 //===----------------------------------------------------------------------===//
Index: llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td
+++ llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td
@@ -114,7 +114,7 @@
 def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
 def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
 def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
-def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
+def LDPC: R6MMR6Rel, LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
 def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6;
 def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
 let DecoderNamespace = "Mips32r6_64r6_GP64" in {
Index: llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt
@@ -141,6 +141,7 @@
 0x60 0x25 0xa6 0x08 # CHECK: cachee 1, 8($5)
 0x00 0x64 0xf1 0x7c # CHECK: wrpgpr $3, $4
 0x00 0x64 0x7b 0x3c # CHECK: wsbh $3, $4
+0x78 0x58 0x00 0x02 # CHECK: ldpc $2, 16
 0x65 0x88 # CHECK: lw $3, 32($gp)
 0x48 0x66 # CHECK: lw $3, 24($sp)
 0x6a 0x12 # CHECK: lw16 $4, 8($17)
Index: llvm/trunk/test/MC/Mips/micromips64r6/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/valid.s
+++ llvm/trunk/test/MC/Mips/micromips64r6/valid.s
@@ -21,6 +21,7 @@
         dextm $9, $6, 3, 39      # CHECK: dextm $9, $6, 3, 39 # encoding: [0x59,0x26,0x30,0xe4]
         dextu $9, $6, 35, 7      # CHECK: dextu $9, $6, 35, 7  # encoding: [0x59,0x26,0x30,0xd4]
         dalign $4, $2, $3, 5     # CHECK: dalign $4, $2, $3, 5  # encoding: [0x58,0x43,0x25,0x1c]
+        ldpc $2, 16              # CHECK: ldpc $2, 16           # encoding: [0x78,0x58,0x00,0x02]
         lw $3, 32($gp)           # CHECK: lw $3, 32($gp)        # encoding: [0x65,0x88]
         lw $3, 24($sp)           # CHECK: lw $3, 24($sp)        # encoding: [0x48,0x66]
         lw16 $4, 8($17)          # CHECK: lw16 $4, 8($17)       # encoding: [0x6a,0x12]


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