[llvm] r266980 - [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructions
Zlatko Buljan via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 21 04:32:42 PDT 2016
Author: zbuljan
Date: Thu Apr 21 06:32:40 2016
New Revision: 266980
URL: http://llvm.org/viewvc/llvm-project?rev=266980&view=rev
Log:
[mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructions
Differential Revision: http://reviews.llvm.org/D18855
Modified:
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt
llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
llvm/trunk/test/MC/Mips/micromips64r6/invalid.s
llvm/trunk/test/MC/Mips/micromips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=266980&r1=266979&r2=266980&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Apr 21 06:32:40 2016
@@ -2077,11 +2077,12 @@ def JALR_HB : JALR_HB_DESC, JALR_HB_ENC,
class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
FrmOther, asmstr>;
-def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
-def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
-def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
-def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
-
+let AdditionalPredicates = [NotInMicroMips] in {
+ def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
+ def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
+ def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
+ def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
+}
class CacheOp<string instr_asm, Operand MemOpnd> :
InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
!strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther,
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt?rev=266980&r1=266979&r2=266980&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt Thu Apr 21 06:32:40 2016
@@ -298,3 +298,7 @@
0x00 0x22 0x08 0xf4 # CHECK: mfhc0 $1, $2, 1
0x54 0x06 0x30 0x3b # CHECK: mfhc1 $zero, $f6
0x02 0xf0 0x8d 0x3c # CHECK: mfhc2 $23, $16
+0x00 0x00 0x03 0x7c # CHECK: tlbp
+0x00 0x00 0x13 0x7c # CHECK: tlbr
+0x00 0x00 0x23 0x7c # CHECK: tlbwi
+0x00 0x00 0x33 0x7c # CHECK: tlbwr
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt?rev=266980&r1=266979&r2=266980&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt Thu Apr 21 06:32:40 2016
@@ -225,3 +225,7 @@
0x5f 0x02 0x46 0x9f # CHECK: daddiu $24, $2, 18079
0x5c 0x63 0xff 0xfb # CHECK: daddiu $3, $3, -5
0x5c 0x64 0xff 0xfb # CHECK: daddiu $3, $4, -5
+0x00 0x00 0x03 0x7c # CHECK: tlbp
+0x00 0x00 0x13 0x7c # CHECK: tlbr
+0x00 0x00 0x23 0x7c # CHECK: tlbwi
+0x00 0x00 0x33 0x7c # CHECK: tlbwr
Modified: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/invalid.s?rev=266980&r1=266979&r2=266980&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s Thu Apr 21 06:32:40 2016
@@ -137,3 +137,15 @@
swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
+ tlbp $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ tlbp 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ tlbp $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ tlbr $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ tlbr 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ tlbr $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ tlbwi $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+ tlbwi 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+ tlbwi $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+ tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+ tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+ tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=266980&r1=266979&r2=266980&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Thu Apr 21 06:32:40 2016
@@ -309,3 +309,7 @@
mfhc0 $1, $2, 1 # CHECK: mfhc0 $1, $2, 1 # encoding: [0x00,0x22,0x08,0xf4]
mfhc1 $zero, $f6 # CHECK: mfhc1 $zero, $f6 # encoding: [0x54,0x06,0x30,0x3b]
mfhc2 $23, $16 # CHECK: mfhc2 $23, $16 # encoding: [0x02,0xf0,0x8d,0x3c]
+ tlbp # CHECK: tlbp # encoding: [0x00,0x00,0x03,0x7c]
+ tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c]
+ tlbwi # CHECK: tlbwi # encoding: [0x00,0x00,0x23,0x7c]
+ tlbwr # CHECK: tlbwr # encoding: [0x00,0x00,0x33,0x7c]
Modified: llvm/trunk/test/MC/Mips/micromips64r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/invalid.s?rev=266980&r1=266979&r2=266980&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/invalid.s Thu Apr 21 06:32:40 2016
@@ -162,3 +162,15 @@
swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
+ tlbp $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ tlbp 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ tlbp $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ tlbr $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ tlbr 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ tlbr $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ tlbwi $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+ tlbwi 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+ tlbwi $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+ tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+ tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+ tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/Mips/micromips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/valid.s?rev=266980&r1=266979&r2=266980&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/valid.s Thu Apr 21 06:32:40 2016
@@ -220,5 +220,9 @@ a:
daddu $24, $2, 18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x5f,0x02,0x46,0x9f]
dsubu $3, 5 # CHECK: daddiu $3, $3, -5 # encoding: [0x5c,0x63,0xff,0xfb]
dsubu $3, $4, 5 # CHECK: daddiu $3, $4, -5 # encoding: [0x5c,0x64,0xff,0xfb]
+ tlbp # CHECK: tlbp # encoding: [0x00,0x00,0x03,0x7c]
+ tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c]
+ tlbwi # CHECK: tlbwi # encoding: [0x00,0x00,0x23,0x7c]
+ tlbwr # CHECK: tlbwr # encoding: [0x00,0x00,0x33,0x7c]
1:
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