[llvm] r266861 - [mips][microMIPS]Implement CFC*, CTC* and LDC* instructions
Hrvoje Varga via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 19 23:34:50 PDT 2016
Author: hvarga
Date: Wed Apr 20 01:34:48 2016
New Revision: 266861
URL: http://llvm.org/viewvc/llvm-project?rev=266861&view=rev
Log:
[mips][microMIPS]Implement CFC*, CTC* and LDC* instructions
Differential Revision: http://reviews.llvm.org/D18640
Modified:
llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
llvm/trunk/test/MC/Mips/mips32r5/invalid.s
llvm/trunk/test/MC/Mips/mips64r5/invalid.s
llvm/trunk/test/MC/Mips/mips64r6/invalid.s
Modified: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=266861&r1=266860&r2=266861&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Wed Apr 20 01:34:48 2016
@@ -341,6 +341,10 @@ static DecodeStatus DecodeFMem(MCInst &I
uint64_t Address,
const void *Decoder);
+static DecodeStatus DecodeFMemMMR6(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder);
@@ -353,6 +357,10 @@ static DecodeStatus DecodeFMemCop2R6(MCI
uint64_t Address,
const void *Decoder);
+static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
unsigned Insn,
uint64_t Address,
@@ -1588,6 +1596,22 @@ static DecodeStatus DecodeFMem(MCInst &I
return MCDisassembler::Success;
}
+static DecodeStatus DecodeFMemMMR6(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ int Offset = SignExtend32<16>(Insn & 0xffff);
+ unsigned Base = fieldFromInstruction(Insn, 16, 5);
+ unsigned Reg = fieldFromInstruction(Insn, 21, 5);
+
+ Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
+ Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
+
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
+
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeFMem2(MCInst &Inst,
unsigned Insn,
uint64_t Address,
@@ -1634,6 +1658,22 @@ static DecodeStatus DecodeFMemCop2R6(MCI
Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
+
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
+
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ int Offset = SignExtend32<11>(Insn & 0x07ff);
+ unsigned Reg = fieldFromInstruction(Insn, 21, 5);
+ unsigned Base = fieldFromInstruction(Insn, 16, 5);
+
+ Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
+ Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Base));
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp?rev=266861&r1=266860&r2=266861&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp Wed Apr 20 01:34:48 2016
@@ -756,6 +756,19 @@ getMemEncodingMMImm9(const MCInst &MI, u
}
unsigned MipsMCCodeEmitter::
+getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ // Base register is encoded in bits 20-16, offset is encoded in bits 10-0.
+ assert(MI.getOperand(OpNo).isReg());
+ unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
+ STI) << 16;
+ unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
+
+ return (OffBits & 0x07FF) | RegBits;
+}
+
+unsigned MipsMCCodeEmitter::
getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h?rev=266861&r1=266860&r2=266861&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h Wed Apr 20 01:34:48 2016
@@ -183,6 +183,9 @@ public:
unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
+ unsigned getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td?rev=266861&r1=266860&r2=266861&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td Wed Apr 20 01:34:48 2016
@@ -916,3 +916,35 @@ class POOL32A_MFTC2_FM_MMR6<string instr
let Inst{15-6} = funct;
let Inst{5-0} = 0b111100;
}
+
+class LDWC1_SDWC1_FM_MMR6<string instr_asm, bits<6> funct>
+ : MMR6Arch<instr_asm> {
+ bits<5> ft;
+ bits<21> addr;
+ bits<5> base = addr{20-16};
+ bits<16> offset = addr{15-0};
+
+ bits<32> Inst;
+
+ let Inst{31-26} = funct;
+ let Inst{25-21} = ft;
+ let Inst{20-16} = base;
+ let Inst{15-0} = offset;
+}
+
+class POOL32B_LDWC2_SDWC2_FM_MMR6<string instr_asm, bits<4> funct>
+ : MMR6Arch<instr_asm>, MipsR6Inst {
+ bits<5> rt;
+ bits<21> addr;
+ bits<5> base = addr{20-16};
+ bits<11> offset = addr{10-0};
+
+ bits<32> Inst;
+
+ let Inst{31-26} = 0b001000;
+ let Inst{25-21} = rt;
+ let Inst{20-16} = base;
+ let Inst{15-12} = funct;
+ let Inst{11} = 0;
+ let Inst{10-0} = offset;
+}
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=266861&r1=266860&r2=266861&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Wed Apr 20 01:34:48 2016
@@ -47,6 +47,10 @@ class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_B
class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
+class CFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"cfc1", 0b01000000>;
+class CFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"cfc2", 0b1100110100>;
+class CTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"ctc1", 0b01100000>;
+class CTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"ctc2", 0b1101110100>;
class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
@@ -62,6 +66,8 @@ class JIALC_MMR6_ENC : JMP_IDX_COMPACT_F
class JIC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101000>;
class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
+class LDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"ldc1", 0b101111>;
+class LDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"ldc2", 0b0010>;
class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>;
class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>;
@@ -664,6 +670,48 @@ class MFHC1_D64_MMR6_DESC : MFC1_MMR6_DE
II_MFHC1>, HARDFLOAT, FGR_64;
class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd>;
+class CFC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>,
+ HARDFLOAT;
+class CFC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"cfc2", GPR32Opnd, COP2Opnd>;
+class CTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>,
+ HARDFLOAT;
+class CTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"ctc2", COP2Opnd, GPR32Opnd>;
+
+class LDWC1_DESC_BASE<string opstr, RegisterOperand RC, InstrItinClass Itin,
+ SDPatternOperator OpNode = null_frag> : MipsR6Inst,
+ HARDFLOAT {
+ dag InOperandList = (ins mem_mm_16:$addr);
+ dag OutOperandList = (outs RC:$ft);
+ string AsmString = !strconcat(opstr, "\t$ft, $addr");
+ list<dag> Pattern = [(set RC:$ft, (OpNode addrDefault:$addr))];
+ Format f = FrmFI;
+ InstrItinClass Itinerary = Itin;
+ string BaseOpcode = opstr;
+ bit mayLoad = 1;
+ let DecoderMethod = "DecodeFMemMMR6";
+}
+class LDC1_D32_MMR6_DESC : LDWC1_DESC_BASE<
+ "ldc1", AFGR64Opnd, II_LDC1, load>, FGR_32;
+class LDC1_D64_MMR6_DESC : LDWC1_DESC_BASE<
+ "ldc1", FGR64Opnd, II_LDC1, load>, FGR_64;
+
+class COP2LD_MMR6_DESC_BASE<string opstr, RegisterOperand COPOpnd,
+ InstrItinClass Itin,
+ SDPatternOperator OpNode = null_frag> {
+ dag OutOperandList = (outs COPOpnd:$rt);
+ dag InOperandList = (ins mem_mm_11:$addr);
+ string AsmString = !strconcat(opstr, "\t$rt, $addr");
+ list<dag> Pattern = [(set COPOpnd:$rt, (OpNode addrDefault:$addr))];
+ Format f = FrmFI;
+ InstrItinClass Itinerary = Itin;
+ string BaseOpcode = opstr;
+ bit mayLoad = 1;
+ string DecoderMethod = "DecodeFMemCop2MMR6";
+}
+
+class LDC2_MMR6_DESC : COP2LD_MMR6_DESC_BASE<"ldc2", COP2Opnd, NoItinerary,
+ load>;
+
/// Floating Point Instructions
class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
InstrItinClass Itin, bit isComm,
@@ -1104,6 +1152,10 @@ def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MM
ISA_MICROMIPS32R6;
def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
+def CFC1_MMR6 : StdMMR6Rel, CFC1_MMR6_DESC, CFC1_MMR6_ENC, ISA_MICROMIPS32R6;
+def CFC2_MMR6 : StdMMR6Rel, CFC2_MMR6_ENC, CFC2_MMR6_DESC, ISA_MICROMIPS32R6;
+def CTC1_MMR6 : StdMMR6Rel, CTC1_MMR6_DESC, CTC1_MMR6_ENC, ISA_MICROMIPS32R6;
+def CTC2_MMR6 : StdMMR6Rel, CTC2_MMR6_ENC, CTC2_MMR6_DESC, ISA_MICROMIPS32R6;
def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
@@ -1122,6 +1174,13 @@ def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC,
def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
ISA_MICROMIPS32R6;
+def LDC1_D32_MMR6 : StdMMR6Rel, LDC1_D32_MMR6_DESC, LDC1_MMR6_ENC,
+ ISA_MICROMIPS32R6;
+let DecoderNamespace = "MicroMips32r6FP64" in {
+ def LDC1_D64_MMR6 : LDC1_D64_MMR6_DESC, LDC1_MMR6_ENC,
+ ISA_MICROMIPS32R6;
+}
+def LDC2_MMR6 : StdMMR6Rel, LDC2_MMR6_ENC, LDC2_MMR6_DESC, ISA_MICROMIPS32R6;
def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6;
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td?rev=266861&r1=266860&r2=266861&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td Wed Apr 20 01:34:48 2016
@@ -20,7 +20,6 @@ def FSUB_MM : MMRel, ADDS_FT<"sub.d", A
def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM_MM<0x27>;
def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>,
LW_FM_MM<0x26>;
-def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM_MM<0x2f>;
def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>,
LW_FM_MM<0x2e>;
def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>,
@@ -147,4 +146,9 @@ let AdditionalPredicates = [InMicroMips]
MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32;
def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32;
+ def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>,
+ LW_FM_MM<0x2f>, FGR_32 {
+ let DecoderNamespace = "MicroMips";
+ let DecoderMethod = "DecodeFMemMMR6";
+ }
}
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=266861&r1=266860&r2=266861&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Wed Apr 20 01:34:48 2016
@@ -96,6 +96,14 @@ def mem_mm_9 : Operand<i32> {
let OperandType = "OPERAND_MEMORY";
}
+def mem_mm_11 : Operand<i32> {
+ let PrintMethod = "printMemOperand";
+ let MIOperandInfo = (ops ptr_rc, simm11);
+ let EncoderMethod = "getMemEncodingMMImm11";
+ let ParserMatchClass = MipsMemSimm11AsmOperand;
+ let OperandType = "OPERAND_MEMORY";
+}
+
def mem_mm_12 : Operand<i32> {
let PrintMethod = "printMemOperand";
let MIOperandInfo = (ops ptr_rc, simm12);
Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td?rev=266861&r1=266860&r2=266861&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td Wed Apr 20 01:34:48 2016
@@ -755,7 +755,9 @@ let AdditionalPredicates = [NotInMicroMi
def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;
def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
-def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
+let AdditionalPredicates = [NotInMicroMips] in {
+ def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
+}
def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6;
def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;
def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=266861&r1=266860&r2=266861&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Wed Apr 20 01:34:48 2016
@@ -404,14 +404,17 @@ def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opn
def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>;
let DecoderNamespace = "Mips64" in {
- def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>, ISA_MIPS2,
- FGR_64;
+ let AdditionalPredicates = [NotInMicroMips] in {
+ def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>,
+ ISA_MIPS2, FGR_64;
+ }
def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, ISA_MIPS2,
FGR_64;
}
-
-def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>,
- ISA_MIPS2, FGR_32;
+let AdditionalPredicates = [NotInMicroMips] in {
+ def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>,
+ LW_FM<0x35>, ISA_MIPS2, FGR_32;
+}
def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>,
ISA_MIPS2, FGR_32;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=266861&r1=266860&r2=266861&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Apr 20 01:34:48 2016
@@ -1749,7 +1749,7 @@ def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoIt
ISA_MIPS1_NOT_32R6_64R6;
def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
ISA_MIPS1_NOT_32R6_64R6;
-def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
+def LDC2 : StdMMR6Rel, LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
ISA_MIPS2_NOT_32R6_64R6;
def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
ISA_MIPS2_NOT_32R6_64R6;
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt?rev=266861&r1=266860&r2=266861&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt Wed Apr 20 01:34:48 2016
@@ -53,6 +53,10 @@
0x20 0x25 0x60 0x08 # CHECK: cache 1, 8($5)
0x01 0x65 0x4b 0x3c # CHECK: clo $11, $5
0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
+0x54 0x22 0x10 0x3b # CHECK: cfc1 $1, $2
+0x00 0x64 0xcd 0x3c # CHECK: cfc2 $3, $4
+0x54 0xa6 0x18 0x3b # CHECK: ctc1 $5, $6
+0x00 0xe8 0xdd 0x3c # CHECK: ctc2 $7, $8
0x00 0x00 0xe3 0x7c # CHECK: deret
0x00 0xa4 0x19 0x18 # CHECK: div $3, $4, $5
0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5
@@ -63,6 +67,8 @@
0x00 0x01 0xf3 0x7c # CHECK: eretnc
0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256
+0xbd 0x0a 0x01 0x2c # CHECK: ldc1 $f8, 300($10)
+0x21 0x6c 0x23 0xff # CHECK: ldc2 $11, 1023($12)
0x78 0x48 0x00 0x43 # CHECK: lwpc $2, 268
0x00 0x43 0x26 0x0f # CHECK: lsa $2, $3, $4, 4
0x00 0xa4 0x19 0x58 # CHECK: mod $3, $4, $5
Modified: llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s?rev=266861&r1=266860&r2=266861&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s Wed Apr 20 01:34:48 2016
@@ -7,6 +7,8 @@
# the diagnostic for the 10-bit form. This isn't exactly wrong but it is
# misleading. Ideally, we'd emit every way to achieve a valid match instead
# of picking only one.
+ ldc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ldc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
teq $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
teq $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
teq $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=266861&r1=266860&r2=266861&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Wed Apr 20 01:34:48 2016
@@ -39,6 +39,10 @@
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08]
clo $11, $a1 # CHECK: clo $11, $5 # encoding: [0x01,0x65,0x4b,0x3c]
clz $sp, $gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
+ cfc1 $1, $2 # CHECK: cfc1 $1, $2 # encoding: [0x54,0x22,0x10,0x3b]
+ cfc2 $3, $4 # CHECK: cfc2 $3, $4 # encoding: [0x00,0x64,0xcd,0x3c]
+ ctc1 $5, $6 # CHECK: ctc1 $5, $6 # encoding: [0x54,0xa6,0x18,0x3b]
+ ctc2 $7, $8 # CHECK: ctc2 $7, $8 # encoding: [0x00,0xe8,0xdd,0x3c]
div $3, $4, $5 # CHECK: div $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x18]
divu $3, $4, $5 # CHECK: divu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x98]
ehb # CHECK: ehb # encoding: [0x00,0x00,0x18,0x00]
@@ -55,6 +59,8 @@
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00]
jrc16 $9 # CHECK: jrc16 $9 # encoding: [0x45,0x23]
jrcaddiusp 20 # CHECK: jrcaddiusp 20 # encoding: [0x44,0xb3]
+ ldc1 $f8, 300($10) # CHECK: ldc1 $f8, 300($10) # encoding: [0xbd,0x0a,0x01,0x2c]
+ ldc2 $11, 1023($12) # CHECK: ldc2 $11, 1023($12) # encoding: [0x21,0x6c,0x23,0xff]
lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x24,0x0f]
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43]
lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
Modified: llvm/trunk/test/MC/Mips/mips32r5/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r5/invalid.s?rev=266861&r1=266860&r2=266861&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r5/invalid.s Wed Apr 20 01:34:48 2016
@@ -10,8 +10,8 @@
cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
- pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
- pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
+ ldc2 $11, -32769($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ ldc2 $11, 32768($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mtc2 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
@@ -20,3 +20,5 @@
mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mfc2 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mfc2 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
+ pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
+ pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
Modified: llvm/trunk/test/MC/Mips/mips64r5/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/invalid.s?rev=266861&r1=266860&r2=266861&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r5/invalid.s Wed Apr 20 01:34:48 2016
@@ -10,11 +10,13 @@
cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
- jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
- jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
- pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
- pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
+ jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
+ jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
+ ldc2 $11, -32769($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ ldc2 $11, 32768($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
+ pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
Modified: llvm/trunk/test/MC/Mips/mips64r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/invalid.s?rev=266861&r1=266860&r2=266861&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/invalid.s Wed Apr 20 01:34:48 2016
@@ -12,7 +12,6 @@ local_label:
align $4, $2, $3, 4 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate
jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
- ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
break -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
break -1, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
@@ -39,6 +38,8 @@ local_label:
drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
+ ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ldc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
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