[PATCH] D17989: [mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions

[Simon Dardis via llvm-commits]

sdardis requested changes to this revision.
sdardis added a comment.
This revision now requires changes to proceed.

Comments inlined. Can you rebase and repost?


================
Comment at: test/CodeGen/Mips/llvm-ir/ashr.ll:229
@@ -194,1 +228,3 @@
 
+  ; MM:             lw        $25, %call16(__ashrti3)($2)
+
----------------
Since you've posted this patch, the LLVM backend for MIPS was changed to use the static relocation model, so this should be:
    jals      __ashrti3

================
Comment at: test/MC/Disassembler/Mips/micromips32r3/valid-el.txt:192-200
@@ -191,1 +191,10 @@
 0x44 0x60 0x08 0xac # CHECK: sce $2, 8($4)
+0x65 0x00 0x10 0x10 # CHECK: sllv $2, $3, $5
+0x65 0x00 0x90 0x10 # CHECK: srav $2, $3, $5
+0x65 0x00 0x50 0x10 # CHECK: srlv $2, $3, $5
+0x43 0x00 0x10 0x10 # CHECK: sllv $2, $2, $3
+0x43 0x00 0x90 0x10 # CHECK: srav $2, $2, $3
+0x43 0x00 0x50 0x10 # CHECK: srlv $2, $2, $3
+0x63 0x00 0x00 0x38 # CHECK: sll $3, $3, 7
+0x63 0x00 0x80 0x38 # CHECK: sra $3, $3, 7
+0x63 0x00 0x40 0x38 # CHECK: srl $3, $3, 7
----------------
sllv, srav and srlv appear twice here. Once is enough. There are more occurrences in the other tests.


http://reviews.llvm.org/D17989