[PATCH] D19061: [ARM] Add support for the X asm constraint

[silviu.baranga@arm.com via llvm-commits]

sbaranga added a comment.

In http://reviews.llvm.org/D19061#400041, @rengolin wrote:

> Do'h! I missed the PR reference, my apologies.
>
> Though, wrt the blog post, I think it's a very lean source for such a generic case like this. I suggest you try to use the constraint on GCC and come up with a general description for its behaviour, what's allowed and what's not. Maybe even talk to a few GCC engineers once you have a better idea, and then be able to accurately describe what we want to implement.
>
> Without that, it'll be hard to review the patch, and adding a hack to make your specific use case pass wouldn't be very constructive, either. :)
>
> cheers,
> --renato


Sure!

Cheers,
Silviu


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:11457
@@ +11456,3 @@
+      ConstraintVT.getSizeInBits() == 128))
+    return "w";
+
----------------
rengolin wrote:
> sbaranga wrote:
> > rengolin wrote:
> > > No "t" for 32-bit FP registers?
> > Why "t" (wouldn't "w" be enough)? 
> "t" would select an S register, while "w" would select a D reg.
> 
> If this is "anything", shouldn't it also allow immediate values and expressions?
Our 'w' matching strategy would also match SPRs, DPRs and QPRs (see getRegForInlineAsmConstraint), based on the size of ConstraintVT. If that fails, the generic getRegForInlineAsmConstraint will still be able to give this a register class.

It does need a regression test though.

Regarding immediates/expressions: at least our implementation doesn't allow it (on any targets). I'll check what gcc does.


http://reviews.llvm.org/D19061