[llvm] r266206 - AArch64: don't create instructions that write to xzr/wzr twice.

[Tim Northover via llvm-commits]

Author: tnorthover
Date: Wed Apr 13 11:25:39 2016
New Revision: 266206

URL: http://llvm.org/viewvc/llvm-project?rev=266206&view=rev
Log:
AArch64: don't create instructions that write to xzr/wzr twice.

These are unpredictable even on AArch64.

Patch by Yichao Yu.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
    llvm/trunk/test/CodeGen/AArch64/arm64-atomic-128.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp?rev=266206&r1=266205&r2=266206&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp Wed Apr 13 11:25:39 2016
@@ -93,6 +93,12 @@ bool AArch64DeadRegisterDefinitions::pro
       DEBUG(dbgs() << "    Ignoring, operand is frame index\n");
       continue;
     }
+    if (MI.definesRegister(AArch64::XZR) || MI.definesRegister(AArch64::WZR)) {
+      // It is not allowed to write to the same register (not even the zero
+      // register) twice in a single instruction.
+      DEBUG(dbgs() << "    Ignoring, XZR or WZR already used by the instruction\n");
+      continue;
+    }
     for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) {
       MachineOperand &MO = MI.getOperand(i);
       if (MO.isReg() && MO.isDead() && MO.isDef()) {
@@ -128,6 +134,8 @@ bool AArch64DeadRegisterDefinitions::pro
         MO.setReg(NewReg);
         DEBUG(MI.print(dbgs()));
         ++NumDeadDefsReplaced;
+        // Only replace one dead register, see check for zero register above.
+        break;
       }
     }
   }

Modified: llvm/trunk/test/CodeGen/AArch64/arm64-atomic-128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-atomic-128.ll?rev=266206&r1=266205&r2=266206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-atomic-128.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-atomic-128.ll Wed Apr 13 11:25:39 2016
@@ -190,7 +190,7 @@ define void @atomic_store_seq_cst(i128 %
 ; CHECK-LABEL: atomic_store_seq_cst:
 ; CHECK-NOT: dmb
 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
-; CHECK: ldaxp xzr, xzr, [x2]
+; CHECK: ldaxp xzr, [[IGNORED:x[0-9]+]], [x2]
 ; CHECK: stlxp [[SUCCESS:w[0-9]+]], x0, x1, [x2]
 ; CHECK: cbnz [[SUCCESS]], [[LABEL]]
 ; CHECK-NOT: dmb
@@ -202,7 +202,7 @@ define void @atomic_store_release(i128 %
 ; CHECK-LABEL: atomic_store_release:
 ; CHECK-NOT: dmb
 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
-; CHECK: ldxp xzr, xzr, [x2]
+; CHECK: ldxp xzr, [[IGNORED:x[0-9]+]], [x2]
 ; CHECK: stlxp [[SUCCESS:w[0-9]+]], x0, x1, [x2]
 ; CHECK: cbnz [[SUCCESS]], [[LABEL]]
 ; CHECK-NOT: dmb
@@ -214,7 +214,7 @@ define void @atomic_store_relaxed(i128 %
 ; CHECK-LABEL: atomic_store_relaxed:
 ; CHECK-NOT: dmb
 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
-; CHECK: ldxp xzr, xzr, [x2]
+; CHECK: ldxp xzr, [[IGNORED:x[0-9]+]], [x2]
 ; CHECK: stxp [[SUCCESS:w[0-9]+]], x0, x1, [x2]
 ; CHECK: cbnz [[SUCCESS]], [[LABEL]]
 ; CHECK-NOT: dmb