[PATCH] D18995: [mips] Fix emitAtomicCmpSwapPartword to handle 64 bit pointers correctly

[Daniel Sanders via llvm-commits]

dsanders added inline comments.

================
Comment at: lib/Target/Mips/MipsISelLowering.cpp:1488-1489
@@ -1484,4 +1487,4 @@
     .addReg(Mips::ZERO).addImm(-4);
-  BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
+  BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
     .addReg(Ptr).addReg(MaskLSB2);
   BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
----------------
dsanders wrote:
> On N64, this code can produce an AND64 with a GPR64 result, one GPR64 operand (Ptr), and a GPR32 operand (MaskLSB2). This contradicts the instruction definition for AND64 which expects the result and both operands to be GPR64.
> 
> Adding -verify-machineinstrs to your llc command will report the places where register classes are used incorrectly. You may also need to use SUBREG_TO_REG or EXTRACT_SUBREG to switch between register classes in some places.
> Adding -verify-machineinstrs to your llc command will report the places where register classes are used incorrectly. You may also need to use SUBREG_TO_REG or EXTRACT_SUBREG to switch between register classes in some places.

Sorry, I've made a mistake here. EXTRACT_SUBREG is for an earlier stage of the code generator. At this stage you need to use something like `BuildMI(...).addReg(Reg, 0, Mips::sub_32)` instead.


http://reviews.llvm.org/D18995