[PATCH] D17306: DAGCombiner: Relax alignment restriction when changing load type

[Matt Arsenault via llvm-commits]

arsenm added a comment.

I see 3 more x86 failures on trunk with this.

The first looks like this:
IR (from avx512-mask-op.ll):

  define void @mask8_mem(i8* %ptr) {
    %x = load i8, i8* %ptr, align 4
    %m0 = bitcast i8 %x to <8 x i1>
    %m1 = xor <8 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
    %ret = bitcast <8 x i1> %m1 to i8
    store i8 %ret, i8* %ptr, align 4
    ret void
  }

Before:

  _mask8_mem:                             ## @mask8_mem
  	.cfi_startproc
  ## BB#0:
  	movb	(%rdi), %al
  	kmovw	%eax, %k0
  	knotw	%k0, %k0
  	kmovw	%k0, %eax
  	movb	%al, (%rdi)
  	retq

After:

  _mask8_mem:                             ## @mask8_mem
  	.cfi_startproc
  ## BB#0:
  	movzbw	(%rdi), %ax
  	kmovw	%eax, %k0
  	knotw	%k0, %k0
  	kmovw	%k0, %eax
  	movb	%al, (%rdi)
  	retq

A second looks similar, and another in merge-consecutive-loads-512.ll has one difference of
	vmovdqu32	8(%eax), %zmm0
vs.
	vmovdqu64	8(%eax), %zmm0


http://reviews.llvm.org/D17306