[PATCH] D19017: [x86, InstCombine] fix masked loads pass-through operand to be a zero vector

[Sanjay Patel via llvm-commits]

spatel created this revision.
spatel added reviewers: andreadb, RKSimon, delena.
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This bug was introduced with:
http://reviews.llvm.org/rL262269

AVX masked loads are specified to set vector lanes to zero when the high bit of the mask element for that lane is zero:
"If the mask is 0, the corresponding data element is set to zero in the load form of these instructions, and unmodified in the store form." --Intel manual



http://reviews.llvm.org/D19017

Files:
  lib/Transforms/InstCombine/InstCombineCalls.cpp
  test/Transforms/InstCombine/x86-masked-memops.ll

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