[llvm] r265574 - [RegisterBankInfo] Add a method to get the mapping RegClass -> RegBank.

[Quentin Colombet via llvm-commits]

Author: qcolombet
Date: Wed Apr  6 12:51:41 2016
New Revision: 265574

URL: http://llvm.org/viewvc/llvm-project?rev=265574&view=rev
Log:
[RegisterBankInfo] Add a method to get the mapping RegClass -> RegBank.
This should be TableGen'ed at some point.

Modified:
    llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h

Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h?rev=265574&r1=265573&r2=265574&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h Wed Apr  6 12:51:41 2016
@@ -195,6 +195,23 @@ public:
   /// Get the total number of register banks.
   unsigned getNumRegBanks() const { return NumRegBanks; }
 
+  /// Get a register bank that covers \p RC.
+  ///
+  /// \pre \p RC is a user-defined register class (as opposed as one
+  /// generated by TableGen).
+  ///
+  /// \note The mapping RC -> RegBank could be built while adding the
+  /// coverage for the register banks. However, we do not do it, because,
+  /// at least for now, we only need this information for register classes
+  /// that are used in the description of instruction. In other words,
+  /// there are just a handful of them and we do not want to waste space.
+  ///
+  /// \todo This should be TableGen'ed.
+  virtual const RegisterBank &
+  getRegBankFromRegClass(const TargetRegisterClass &RC) const {
+    llvm_unreachable("The target must override this method");
+  }
+
   /// Get the cost of a copy from \p B to \p A, or put differently,
   /// get the cost of A = COPY B.
   virtual unsigned copyCost(const RegisterBank &A,