[llvm] r265504 - [Power9] Implement copy-paste, msgsync, slb, and stop instructions
Chuang-Yu Cheng via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 5 18:46:45 PDT 2016
Author: cycheng
Date: Tue Apr 5 20:46:45 2016
New Revision: 265504
URL: http://llvm.org/viewvc/llvm-project?rev=265504&view=rev
Log:
[Power9] Implement copy-paste, msgsync, slb, and stop instructions
This patch implements the following BookII and Book III instructions:
- copy copy_first cp_abort paste paste. paste_last
- msgsync
- slbieg slbsync
- stop
Total 10 instructions
Reviewers: nemanjai hfinkel tjablin amehsan kbarton
Modified:
llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/lib/Target/PowerPC/PPCSchedule.td
llvm/trunk/lib/Target/PowerPC/README_P9.txt
llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s
llvm/trunk/test/MC/PowerPC/ppc64-encoding.s
Modified: llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp?rev=265504&r1=265503&r2=265504&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp Tue Apr 5 20:46:45 2016
@@ -1199,6 +1199,29 @@ void PPCAsmParser::ProcessInstruction(MC
}
break;
}
+ case PPC::CP_COPYx:
+ case PPC::CP_COPY_FIRST: {
+ MCInst TmpInst;
+ TmpInst.setOpcode(PPC::CP_COPY);
+ TmpInst.addOperand(Inst.getOperand(0));
+ TmpInst.addOperand(Inst.getOperand(1));
+ TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1));
+
+ Inst = TmpInst;
+ break;
+ }
+ case PPC::CP_PASTEx :
+ case PPC::CP_PASTE_LAST: {
+ MCInst TmpInst;
+ TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ?
+ PPC::CP_PASTE : PPC::CP_PASTEo);
+ TmpInst.addOperand(Inst.getOperand(0));
+ TmpInst.addOperand(Inst.getOperand(1));
+ TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1));
+
+ Inst = TmpInst;
+ break;
+ }
}
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=265504&r1=265503&r2=265504&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Tue Apr 5 20:46:45 2016
@@ -1260,3 +1260,24 @@ def : Pat<(atomic_load_64 xaddr:$src),
def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>;
def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>;
+
+let Predicates = [IsISA3_0] in {
+
+class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,
+ InstrItinClass itin, list<dag> pattern>
+ : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L),
+ !strconcat(opc, " $rA, $rB, $L"), itin, pattern>;
+
+let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
+def CP_COPY8 : X_L1_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>;
+def CP_PASTE8 : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>;
+def CP_PASTE8o : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isDOT;
+}
+
+// SLB Invalidate Entry Global
+def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB),
+ "slbieg $RS, $RB", IIC_SprSLBIEG, []>;
+// SLB Synchronize
+def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
+
+} // IsISA3_0
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td?rev=265504&r1=265503&r2=265504&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td Tue Apr 5 20:46:45 2016
@@ -814,6 +814,17 @@ class X_BF3<bits<6> opcode, bits<10> xo,
let FRB = 0;
}
+// [PO /// L RA RB XO /]
+class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin, list<dag> pattern>
+ : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
+ let BF = 0;
+ let Pattern = pattern;
+
+ bit RC = 0;
+ let Inst{31} = RC;
+}
+
// XX*-Form (VSX)
class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=265504&r1=265503&r2=265504&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Tue Apr 5 20:46:45 2016
@@ -4185,3 +4185,33 @@ def : Pat<(atomic_store_32 iaddr:$ptr, i
def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;
+
+let Predicates = [IsISA3_0] in {
+
+// Copy-Paste Facility
+// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to
+// PASTE for naming consistency.
+let mayLoad = 1 in
+def CP_COPY : X_L1_RA5_RB5<31, 774, "copy" , gprc, IIC_LdStCOPY, []>;
+
+let mayStore = 1 in
+def CP_PASTE : X_L1_RA5_RB5<31, 902, "paste" , gprc, IIC_LdStPASTE, []>;
+
+let mayStore = 1, Defs = [CR0] in
+def CP_PASTEo : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isDOT;
+
+def CP_COPYx : PPCAsmPseudo<"copy $rA, $rB" , (ins gprc:$rA, gprc:$rB)>;
+def CP_PASTEx : PPCAsmPseudo<"paste $rA, $rB", (ins gprc:$rA, gprc:$rB)>;
+def CP_COPY_FIRST : PPCAsmPseudo<"copy_first $rA, $rB",
+ (ins gprc:$rA, gprc:$rB)>;
+def CP_PASTE_LAST : PPCAsmPseudo<"paste_last $rA, $rB",
+ (ins gprc:$rA, gprc:$rB)>;
+def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cp_abort", IIC_SprABORT, []>;
+
+// Message Synchronize
+def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>;
+
+// Power-Saving Mode Instruction:
+def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>;
+
+} // IsISA3_0
Modified: llvm/trunk/lib/Target/PowerPC/PPCSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSchedule.td?rev=265504&r1=265503&r2=265504&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSchedule.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSchedule.td Tue Apr 5 20:46:45 2016
@@ -70,6 +70,8 @@ def IIC_LdStSTFDU : InstrItinClass;
def IIC_LdStSTVEBX : InstrItinClass;
def IIC_LdStSTWCX : InstrItinClass;
def IIC_LdStSync : InstrItinClass;
+def IIC_LdStCOPY : InstrItinClass;
+def IIC_LdStPASTE : InstrItinClass;
def IIC_SprISYNC : InstrItinClass;
def IIC_SprMFSR : InstrItinClass;
def IIC_SprMTMSR : InstrItinClass;
@@ -104,12 +106,17 @@ def IIC_VecVSR : InstrItinClass;
def IIC_SprMTMSRD : InstrItinClass;
def IIC_SprSLIE : InstrItinClass;
def IIC_SprSLBIE : InstrItinClass;
+def IIC_SprSLBIEG : InstrItinClass;
def IIC_SprSLBMTE : InstrItinClass;
def IIC_SprSLBMFEE : InstrItinClass;
def IIC_SprSLBIA : InstrItinClass;
+def IIC_SprSLBSYNC : InstrItinClass;
def IIC_SprTLBIA : InstrItinClass;
def IIC_SprTLBIEL : InstrItinClass;
def IIC_SprTLBIE : InstrItinClass;
+def IIC_SprABORT : InstrItinClass;
+def IIC_SprMSGSYNC : InstrItinClass;
+def IIC_SprSTOP : InstrItinClass;
//===----------------------------------------------------------------------===//
// Processor instruction itineraries.
Modified: llvm/trunk/lib/Target/PowerPC/README_P9.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/README_P9.txt?rev=265504&r1=265503&r2=265504&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/README_P9.txt (original)
+++ llvm/trunk/lib/Target/PowerPC/README_P9.txt Tue Apr 5 20:46:45 2016
@@ -573,3 +573,20 @@ Load Doubleword Monitored (ldmx):
Move to CR from XER Extended (mcrxrx):
- Is there a use for this in LLVM?
+
+Fixed Point Facility:
+
+- Copy-Paste Facility: copy copy_first cp_abort paste paste. paste_last
+ . Use instrinstics:
+ (int_ppc_copy_first i32:$rA, i32:$rB)
+ (int_ppc_copy i32:$rA, i32:$rB)
+
+ (int_ppc_paste i32:$rA, i32:$rB)
+ (int_ppc_paste_last i32:$rA, i32:$rB)
+
+ (int_cp_abort)
+
+- Message Synchronize: msgsync
+- SLB*: slbieg slbsync
+- stop
+ . No instrinstics
Modified: llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt?rev=265504&r1=265503&r2=265504&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt (original)
+++ llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt Tue Apr 5 20:46:45 2016
@@ -669,3 +669,24 @@
# CHECK: mfsrin 10, 12
0x7d 0x40 0x65 0x26
+
+# CHECK: copy 2, 19, 1
+0x7c 0x22 0x9e 0x0c
+
+# CHECK: paste 17, 1, 1
+0x7c 0x31 0x0f 0x0c
+
+# CHECK: cp_abort
+0x7c 0x00 0x06 0x8c
+
+# CHECK: msgsync
+0x7c 0x00 0x06 0xec
+
+# CHECK: slbieg 6, 21
+0x7c 0xc0 0xab 0xa4
+
+# CHECK: slbsync
+0x7c 0x00 0x02 0xa4
+
+# CHECK: stop
+0x4c 0x00 0x02 0xe4
Modified: llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s?rev=265504&r1=265503&r2=265504&view=diff
==============================================================================
--- llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s (original)
+++ llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s Tue Apr 5 20:46:45 2016
@@ -3666,3 +3666,16 @@
# CHECK-LE: attn # encoding: [0x00,0x02,0x00,0x00]
attn
+# Copy-Paste Facility (Extended Mnemonics):
+# CHECK-BE: copy 2, 19, 0 # encoding: [0x7c,0x02,0x9e,0x0c]
+# CHECK-LE: copy 2, 19, 0 # encoding: [0x0c,0x9e,0x02,0x7c]
+ copy 2, 19
+# CHECK-BE: copy 2, 19, 1 # encoding: [0x7c,0x22,0x9e,0x0c]
+# CHECK-LE: copy 2, 19, 1 # encoding: [0x0c,0x9e,0x22,0x7c]
+ copy_first 2, 19
+# CHECK-BE: paste 17, 1, 0 # encoding: [0x7c,0x11,0x0f,0x0c]
+# CHECK-LE: paste 17, 1, 0 # encoding: [0x0c,0x0f,0x11,0x7c]
+ paste 17, 1
+# CHECK-BE: paste. 17, 1, 1 # encoding: [0x7c,0x31,0x0f,0x0d]
+# CHECK-LE: paste. 17, 1, 1 # encoding: [0x0d,0x0f,0x31,0x7c]
+ paste_last 17, 1
Modified: llvm/trunk/test/MC/PowerPC/ppc64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-encoding.s?rev=265504&r1=265503&r2=265504&view=diff
==============================================================================
--- llvm/trunk/test/MC/PowerPC/ppc64-encoding.s (original)
+++ llvm/trunk/test/MC/PowerPC/ppc64-encoding.s Tue Apr 5 20:46:45 2016
@@ -854,3 +854,34 @@
# CHECK-BE: mfsrin 10, 12 # encoding: [0x7d,0x40,0x65,0x26]
# CHECK-LE: mfsrin 10, 12 # encoding: [0x26,0x65,0x40,0x7d]
mfsrin %r10,%r12
+
+# Copy-Paste Facility
+# CHECK-BE: copy 2, 19, 1 # encoding: [0x7c,0x22,0x9e,0x0c]
+# CHECK-LE: copy 2, 19, 1 # encoding: [0x0c,0x9e,0x22,0x7c]
+ copy 2, 19, 1
+# CHECK-BE: paste 17, 1, 1 # encoding: [0x7c,0x31,0x0f,0x0c]
+# CHECK-LE: paste 17, 1, 1 # encoding: [0x0c,0x0f,0x31,0x7c]
+ paste 17, 1, 1
+# CHECK-BE: cp_abort # encoding: [0x7c,0x00,0x06,0x8c]
+# CHECK-LE: cp_abort # encoding: [0x8c,0x06,0x00,0x7c]
+ cp_abort
+
+# Message Synchronize
+# CHECK-BE: msgsync # encoding: [0x7c,0x00,0x06,0xec]
+# CHECK-LE: msgsync # encoding: [0xec,0x06,0x00,0x7c]
+ msgsync
+
+# SLB Invalidate Entry Global
+# CHECK-BE: slbieg 6, 21 # encoding: [0x7c,0xc0,0xab,0xa4]
+# CHECK-LE: slbieg 6, 21 # encoding: [0xa4,0xab,0xc0,0x7c]
+ slbieg 6, 21
+
+# SLB Synchronize
+# CHECK-BE: slbsync # encoding: [0x7c,0x00,0x02,0xa4]
+# CHECK-LE: slbsync # encoding: [0xa4,0x02,0x00,0x7c]
+ slbsync
+
+# Power-Saving Mode Instruction
+# CHECK-BE: stop # encoding: [0x4c,0x00,0x02,0xe4]
+# CHECK-LE: stop # encoding: [0xe4,0x02,0x00,0x4c]
+ stop
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