[PATCH] D18508: Replace at most one dead register with zero register on aarch64

[Yichao Yu via llvm-commits]

yuyichao updated this revision to Diff 52465.
yuyichao added a comment.

Add a check for existing zero register use. There's actually tests for this already but the tests were wrong...

Is there a way to check if the pass keeps `ldxp xzr, x.., [...]` unchanged if the second destination is dead?


http://reviews.llvm.org/D18508

Files:
  lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
  test/CodeGen/AArch64/arm64-atomic-128.ll

Index: test/CodeGen/AArch64/arm64-atomic-128.ll
===================================================================
--- test/CodeGen/AArch64/arm64-atomic-128.ll
+++ test/CodeGen/AArch64/arm64-atomic-128.ll
@@ -190,7 +190,7 @@
 ; CHECK-LABEL: atomic_store_seq_cst:
 ; CHECK-NOT: dmb
 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
-; CHECK: ldaxp xzr, xzr, [x2]
+; CHECK: ldaxp xzr, [[IGNORED:x[0-9]+]], [x2]
 ; CHECK: stlxp [[SUCCESS:w[0-9]+]], x0, x1, [x2]
 ; CHECK: cbnz [[SUCCESS]], [[LABEL]]
 ; CHECK-NOT: dmb
@@ -202,7 +202,7 @@
 ; CHECK-LABEL: atomic_store_release:
 ; CHECK-NOT: dmb
 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
-; CHECK: ldxp xzr, xzr, [x2]
+; CHECK: ldxp xzr, [[IGNORED:x[0-9]+]], [x2]
 ; CHECK: stlxp [[SUCCESS:w[0-9]+]], x0, x1, [x2]
 ; CHECK: cbnz [[SUCCESS]], [[LABEL]]
 ; CHECK-NOT: dmb
@@ -214,7 +214,7 @@
 ; CHECK-LABEL: atomic_store_relaxed:
 ; CHECK-NOT: dmb
 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
-; CHECK: ldxp xzr, xzr, [x2]
+; CHECK: ldxp xzr, [[IGNORED:x[0-9]+]], [x2]
 ; CHECK: stxp [[SUCCESS:w[0-9]+]], x0, x1, [x2]
 ; CHECK: cbnz [[SUCCESS]], [[LABEL]]
 ; CHECK-NOT: dmb
Index: lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
===================================================================
--- lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
+++ lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
@@ -88,6 +88,12 @@
       DEBUG(dbgs() << "    Ignoring, operand is frame index\n");
       continue;
     }
+    if (MI.definesRegister(AArch64::XZR) || MI.definesRegister(AArch64::WZR)) {
+      // It is not allowed to write to the same register (not even the zero
+      // register) twice in a single instruction.
+      DEBUG(dbgs() << "    Ignoring, XZR or WZR already used by the instruction\n");
+      continue;
+    }
     for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) {
       MachineOperand &MO = MI.getOperand(i);
       if (MO.isReg() && MO.isDead() && MO.isDef()) {
@@ -123,6 +129,8 @@
         MO.setReg(NewReg);
         DEBUG(MI.print(dbgs()));
         ++NumDeadDefsReplaced;
+        // Only replace one dead register, see check for zero register above.
+        break;
       }
     }
   }


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