[polly] r265132 - [FIX] Adjust the insert point for non-affine region PHIs

Johannes Doerfert via llvm-commits llvm-commits at lists.llvm.org
Fri Apr 1 04:25:50 PDT 2016


Author: jdoerfert
Date: Fri Apr  1 06:25:47 2016
New Revision: 265132

URL: http://llvm.org/viewvc/llvm-project?rev=265132&view=rev
Log:
[FIX] Adjust the insert point for non-affine region PHIs

  If a non-affine region PHI is generated we should not move the insert
  point prior to the synthezised value in the same block as we might
  split that block at the insert point later on. Only if the incoming
  value should be placed in a different block we should change the
  insertion point.

Added:
    polly/trunk/test/Isl/CodeGen/non-affine-region-exit-phi-incoming-synthesize-2.ll
Modified:
    polly/trunk/lib/CodeGen/BlockGenerators.cpp

Modified: polly/trunk/lib/CodeGen/BlockGenerators.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/CodeGen/BlockGenerators.cpp?rev=265132&r1=265131&r2=265132&view=diff
==============================================================================
--- polly/trunk/lib/CodeGen/BlockGenerators.cpp (original)
+++ polly/trunk/lib/CodeGen/BlockGenerators.cpp Fri Apr  1 06:25:47 2016
@@ -1365,11 +1365,14 @@ void RegionGenerator::addOperandToPHI(Sc
 
     Value *Op = PHI->getIncomingValueForBlock(IncomingBB);
 
-    BasicBlock *OldBlock = Builder.GetInsertBlock();
-    auto OldIP = Builder.GetInsertPoint();
-    Builder.SetInsertPoint(BBCopy->getTerminator());
+    // If the current insert block is different from the PHIs incoming block
+    // change it, otherwise do not.
+    auto IP = Builder.GetInsertPoint();
+    if (IP->getParent() != BBCopy)
+      Builder.SetInsertPoint(BBCopy->getTerminator());
     OpCopy = getNewValue(Stmt, Op, BBCopyMap, LTS, getLoopForStmt(Stmt));
-    Builder.SetInsertPoint(OldBlock, OldIP);
+    if (IP->getParent() != BBCopy)
+      Builder.SetInsertPoint(&*IP);
   } else {
 
     if (PHICopy->getBasicBlockIndex(BBCopy) >= 0)

Added: polly/trunk/test/Isl/CodeGen/non-affine-region-exit-phi-incoming-synthesize-2.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/Isl/CodeGen/non-affine-region-exit-phi-incoming-synthesize-2.ll?rev=265132&view=auto
==============================================================================
--- polly/trunk/test/Isl/CodeGen/non-affine-region-exit-phi-incoming-synthesize-2.ll (added)
+++ polly/trunk/test/Isl/CodeGen/non-affine-region-exit-phi-incoming-synthesize-2.ll Fri Apr  1 06:25:47 2016
@@ -0,0 +1,50 @@
+; RUN: opt %loadPolly -polly-codegen -S < %s | FileCheck %s
+;
+; This caused the code generation to generate invalid code as the same operand
+; of the PHI node in the non-affine region was synthesized at the wrong place.
+; Check we do not generate wrong code.
+;
+; CHECK: polly.start
+;
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+ at connected_passed = external global [256 x i8], align 16
+
+; Function Attrs: norecurse nounwind uwtable
+define void @InitializeZeroMasks() {
+entry:
+  br label %for.end20
+
+for.end20:                                        ; preds = %entry
+  br label %for.body24
+
+for.body24:                                       ; preds = %for.body61.preheader, %for.end20
+  %indvars.iv = phi i64 [ 0, %for.end20 ], [ %indvars.iv.next, %for.body61.preheader ]
+  %arrayidx26 = getelementptr inbounds [256 x i8], [256 x i8]* @connected_passed, i64 0, i64 %indvars.iv
+  store i8 0, i8* %arrayidx26, align 1
+  %0 = trunc i64 %indvars.iv to i32
+  br i1 false, label %for.inc56.4, label %if.then51
+
+if.then51:                                        ; preds = %for.inc56.5, %for.body24
+  %j.342.lcssa = phi i8 [ 7, %for.body24 ], [ %.mux, %for.inc56.5 ]
+  br label %for.body61.preheader
+
+for.body61.preheader:                             ; preds = %for.inc56.5, %if.then51
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond = icmp eq i64 %indvars.iv.next, 256
+  br i1 %exitcond, label %for.end79, label %for.body24
+
+for.end79:                                        ; preds = %for.body61.preheader
+  ret void
+
+for.inc56.4:                                      ; preds = %for.body24
+  br label %for.inc56.5
+
+for.inc56.5:                                      ; preds = %for.inc56.4
+  %and49.6 = and i32 %0, 64
+  %brmerge = or i1 undef, undef
+  %and49.6.lobit = lshr exact i32 %and49.6, 6
+  %.mux = trunc i32 %and49.6.lobit to i8
+  br i1 %brmerge, label %if.then51, label %for.body61.preheader
+}




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