[llvm] r265040 - [ARM] Expand v1i64 and v2i64 ctpop.

Benjamin Kramer via llvm-commits llvm-commits at lists.llvm.org
Thu Mar 31 12:42:05 PDT 2016


Author: d0k
Date: Thu Mar 31 14:42:04 2016
New Revision: 265040

URL: http://llvm.org/viewvc/llvm-project?rev=265040&view=rev
Log:
[ARM] Expand v1i64 and v2i64 ctpop.

The default is legal, which results in 'Cannot select' errors. This is
triggered during selfhost due to a recent cost model change.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/popcnt.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=265040&r1=265039&r2=265040&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Mar 31 14:42:04 2016
@@ -577,6 +577,8 @@ ARMTargetLowering::ARMTargetLowering(con
     setOperationAction(ISD::CTPOP,      MVT::v4i32, Custom);
     setOperationAction(ISD::CTPOP,      MVT::v4i16, Custom);
     setOperationAction(ISD::CTPOP,      MVT::v8i16, Custom);
+    setOperationAction(ISD::CTPOP,      MVT::v1i64, Expand);
+    setOperationAction(ISD::CTPOP,      MVT::v2i64, Expand);
 
     // NEON does not have single instruction CTTZ for vectors.
     setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);

Modified: llvm/trunk/test/CodeGen/ARM/popcnt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/popcnt.ll?rev=265040&r1=265039&r2=265040&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/popcnt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/popcnt.ll Thu Mar 31 14:42:04 2016
@@ -71,12 +71,28 @@ define <4 x i32> @vcntQ32(<4 x i32>* %A)
 	ret <4 x i32> %tmp2
 }
 
+define <1 x i64> @vcnt64(<1 x i64>* %A) nounwind {
+; CHECK-LABEL: vcnt64:
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = call <1 x i64> @llvm.ctpop.v1i64(<1 x i64> %tmp1)
+	ret <1 x i64> %tmp2
+}
+
+define <2 x i64> @vcntQ64(<2 x i64>* %A) nounwind {
+; CHECK-LABEL: vcntQ64:
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %tmp1)
+	ret <2 x i64> %tmp2
+}
+
 declare <8 x i8>  @llvm.ctpop.v8i8(<8 x i8>) nounwind readnone
 declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone
 declare <4 x i16> @llvm.ctpop.v4i16(<4 x i16>) nounwind readnone
 declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) nounwind readnone
 declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone
 declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone
+declare <1 x i64> @llvm.ctpop.v1i64(<1 x i64>) nounwind readnone
+declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone
 
 define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vclz8:




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