[llvm] r265022 - [PowerPC] Basic support for P9 atomic loads and stores
Nemanja Ivanovic via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 31 08:26:38 PDT 2016
Author: nemanjai
Date: Thu Mar 31 10:26:37 2016
New Revision: 265022
URL: http://llvm.org/viewvc/llvm-project?rev=265022&view=rev
Log:
[PowerPC] Basic support for P9 atomic loads and stores
This patch corresponds to review:
http://reviews.llvm.org/D18032
This patch provides asm implementation for the following instructions:
lwat, ldat, stwat, stdat, ldmx, mcrxrx
Modified:
llvm/trunk/lib/Target/PowerPC/PPC.td
llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
llvm/trunk/lib/Target/PowerPC/README_P9.txt
llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt
llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s
llvm/trunk/test/MC/PowerPC/ppc64-encoding.s
Modified: llvm/trunk/lib/Target/PowerPC/PPC.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.td?rev=265022&r1=265021&r2=265022&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPC.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPC.td Thu Mar 31 10:26:37 2016
@@ -163,6 +163,10 @@ def FeatureSlowPOPCNTD : SubtargetFeatur
def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
"Treat vector data stream cache control instructions as deprecated">;
+def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
+ "true",
+ "Enable instructions added in ISA 3.0.">;
+
/* Since new processors generally contain a superset of features of those that
came before them, the idea is to make implementations of new processors
less error prone and easier to read.
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=265022&r1=265021&r2=265022&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Thu Mar 31 10:26:37 2016
@@ -244,12 +244,22 @@ def LDARX : XForm_1<31, 84, (outs g8rc:
// (EH=1 - see Power ISA 2.07 Book II 4.4.2)
def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
"ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT;
+
+let hasExtraDefRegAllocReq = 1 in
+def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC),
+ "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64,
+ Requires<[IsISA3_0]>;
}
let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in
def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
"stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT;
+let mayStore = 1, hasSideEffects = 0 in
+def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC),
+ "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64,
+ Requires<[IsISA3_0]>;
+
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
def TCRETURNdi8 :Pseudo< (outs),
@@ -905,6 +915,10 @@ def LDUX : XForm_1<31, 53, (outs g8rc:$r
"ldux $rD, $addr", IIC_LdStLDUX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">, isPPC64;
+
+def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src),
+ "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64,
+ Requires<[IsISA3_0]>;
}
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td?rev=265022&r1=265021&r2=265022&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td Thu Mar 31 10:26:37 2016
@@ -800,6 +800,20 @@ class X_RD6_IMM8<bits<6> opcode, bits<10
let Inst{31} = XT{5};
}
+// XForm_base_r3xo for instructions such as P9 atomics where we don't want
+// to specify an SDAG pattern for matching.
+class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin>
+ : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, []> {
+}
+
+class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin>
+ : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> {
+ let FRA = 0;
+ let FRB = 0;
+}
+
// XX*-Form (VSX)
class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=265022&r1=265021&r2=265022&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Thu Mar 31 10:26:37 2016
@@ -777,6 +777,7 @@ def NoNaNsFPMath : Predicate<"TM.Options
def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">;
def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">;
def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">;
+def IsISA3_0 : Predicate<"PPCSubTarget->isISA3_0()">;
//===----------------------------------------------------------------------===//
// PowerPC Multiclass Definitions.
@@ -1574,6 +1575,13 @@ def LHARXL : XForm_1<31, 116, (outs gpr
def LWARXL : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
"lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT;
+
+// The atomic instructions use the destination register as well as the next one
+// or two registers in order (modulo 31).
+let hasExtraSrcRegAllocReq = 1 in
+def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC),
+ "lwat $rD, $rA, $FC", IIC_LdStLoad>,
+ Requires<[IsISA3_0]>;
}
let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in {
@@ -1589,6 +1597,11 @@ def STWCX : XForm_1<31, 150, (outs), (in
"stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
}
+let mayStore = 1, hasSideEffects = 0 in
+def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
+ "stwat $rS, $rA, $FC", IIC_LdStStore>,
+ Requires<[IsISA3_0]>;
+
let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
@@ -2359,6 +2372,9 @@ def MFCR : XFXForm_3<31, 19, (outs gprc:
"mfcr $rT", IIC_SprMFCR>,
PPC970_MicroCode, PPC970_Unit_CRU;
} // hasExtraSrcRegAllocReq = 1
+
+def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins),
+ "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>;
} // hasSideEffects = 0
// Pseudo instruction to perform FADD in round-to-zero mode.
Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp?rev=265022&r1=265021&r2=265022&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp Thu Mar 31 10:26:37 2016
@@ -104,6 +104,7 @@ void PPCSubtarget::initializeEnvironment
HasHTM = false;
HasFusion = false;
HasFloat128 = false;
+ IsISA3_0 = false;
HasPOPCNTD = POPCNTD_Unavailable;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h?rev=265022&r1=265021&r2=265022&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h Thu Mar 31 10:26:37 2016
@@ -130,6 +130,7 @@ protected:
bool HasHTM;
bool HasFusion;
bool HasFloat128;
+ bool IsISA3_0;
POPCNTDKind HasPOPCNTD;
@@ -272,6 +273,7 @@ public:
bool hasHTM() const { return HasHTM; }
bool hasFusion() const { return HasFusion; }
bool hasFloat128() const { return HasFloat128; }
+ bool isISA3_0() const { return IsISA3_0; }
POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
Modified: llvm/trunk/lib/Target/PowerPC/README_P9.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/README_P9.txt?rev=265022&r1=265021&r2=265022&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/README_P9.txt (original)
+++ llvm/trunk/lib/Target/PowerPC/README_P9.txt Thu Mar 31 10:26:37 2016
@@ -558,3 +558,18 @@ VSX:
- Load Vector Word & Splat Indexed: lxvwsx
. Likely needs an intrinsic
. (set v?:$XT, (int_ppc_vsx_lxvwsx xoaddr:$src))
+
+Atomic operations (l[dw]at, st[dw]at):
+- Provide custom lowering for common atomic operations to use these
+ instructions with the correct Function Code
+- Ensure the operands are in the correct register (i.e. RT+1, RT+2)
+- Provide builtins since not all FC's necessarily have an existing LLVM
+ atomic operation
+
+Load Doubleword Monitored (ldmx):
+- Investigate whether there are any uses for this. It seems to be related to
+ Garbage Collection so it isn't likely to be all that useful for most
+ languages we deal with.
+
+Move to CR from XER Extended (mcrxrx):
+- Is there a use for this in LLVM?
Modified: llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt?rev=265022&r1=265021&r2=265022&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt (original)
+++ llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt Thu Mar 31 10:26:37 2016
@@ -33,6 +33,12 @@
# CHECK: stdcx. 2, 3, 4
0x7c 0x43 0x21 0xad
+# CHECK: stwat 2, 3, 28
+0x7c 0x43 0xe5 0x8c
+
+# CHECK: stdat 2, 3, 28
+0x7c 0x43 0xe5 0xcc
+
# CHECK: ptesync
0x7c 0x40 0x04 0xac
@@ -72,6 +78,12 @@
# CHECK: ldarx 2, 3, 4, 1
0x7c 0x43 0x20 0xa9
+# CHECK: lwat 2, 3, 28
+0x7c 0x43 0xe4 0x8c
+
+# CHECK: ldat 2, 3, 28
+0x7c 0x43 0xe4 0xcc
+
# CHECK: sync
0x7c 0x00 0x04 0xac
Modified: llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt?rev=265022&r1=265021&r2=265022&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt (original)
+++ llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt Thu Mar 31 10:26:37 2016
@@ -151,6 +151,9 @@
# CHECK: ldux 2, 3, 4
0x7c 0x43 0x20 0x6a
+# CHECK: ldmx 2, 3, 4
+0x7c 0x43 0x22 0x6a
+
# CHECK: stb 2, 128(4)
0x98 0x44 0x00 0x80
@@ -658,7 +661,11 @@
# CHECK: mfocrf 16, 8
0x7e 0x10 0x80 0x26
+# CHECK: mcrxrx 7
+0x7f 0x80 0x04 0x80
+
# CHECK: mtsrin 10, 12
0x7d 0x40 0x61 0xe4
+
# CHECK: mfsrin 10, 12
0x7d 0x40 0x65 0x26
Modified: llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s?rev=265022&r1=265021&r2=265022&view=diff
==============================================================================
--- llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s (original)
+++ llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s Thu Mar 31 10:26:37 2016
@@ -73,10 +73,19 @@
# CHECK-BE: stwcx. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x2d]
# CHECK-LE: stwcx. 2, 3, 4 # encoding: [0x2d,0x21,0x43,0x7c]
stwcx. 2, 3, 4
+
# CHECK-BE: stdcx. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xad]
# CHECK-LE: stdcx. 2, 3, 4 # encoding: [0xad,0x21,0x43,0x7c]
stdcx. 2, 3, 4
+# CHECK-BE: stwat 2, 3, 28 # encoding: [0x7c,0x43,0xe5,0x8c]
+# CHECK-LE: stwat 2, 3, 28 # encoding: [0x8c,0xe5,0x43,0x7c]
+ stwat 2, 3, 28
+
+# CHECK-BE: stdat 2, 3, 28 # encoding: [0x7c,0x43,0xe5,0xcc]
+# CHECK-LE: stdat 2, 3, 28 # encoding: [0xcc,0xe5,0x43,0x7c]
+ stdat 2, 3, 28
+
# CHECK-BE: ptesync # encoding: [0x7c,0x40,0x04,0xac]
# CHECK-LE: ptesync # encoding: [0xac,0x04,0x40,0x7c]
sync 2
@@ -131,6 +140,14 @@
# CHECK-LE: ldarx 2, 3, 4, 1 # encoding: [0xa9,0x20,0x43,0x7c]
ldarx 2, 3, 4, 1
+# CHECK-BE: lwat 2, 3, 28 # encoding: [0x7c,0x43,0xe4,0x8c]
+# CHECK-LE: lwat 2, 3, 28 # encoding: [0x8c,0xe4,0x43,0x7c]
+ lwat 2, 3, 28
+
+# CHECK-BE: ldat 2, 3, 28 # encoding: [0x7c,0x43,0xe4,0xcc]
+# CHECK-LE: ldat 2, 3, 28 # encoding: [0xcc,0xe4,0x43,0x7c]
+ ldat 2, 3, 28
+
# CHECK-BE: sync # encoding: [0x7c,0x00,0x04,0xac]
# CHECK-LE: sync # encoding: [0xac,0x04,0x00,0x7c]
sync
Modified: llvm/trunk/test/MC/PowerPC/ppc64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-encoding.s?rev=265022&r1=265021&r2=265022&view=diff
==============================================================================
--- llvm/trunk/test/MC/PowerPC/ppc64-encoding.s (original)
+++ llvm/trunk/test/MC/PowerPC/ppc64-encoding.s Thu Mar 31 10:26:37 2016
@@ -197,6 +197,9 @@
# CHECK-BE: ldux 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x6a]
# CHECK-LE: ldux 2, 3, 4 # encoding: [0x6a,0x20,0x43,0x7c]
ldux 2, 3, 4
+# CHECK-BE: ldmx 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x6a]
+# CHECK-LE: ldmx 2, 3, 4 # encoding: [0x6a,0x22,0x43,0x7c]
+ ldmx 2, 3, 4
# Fixed-point store instructions
@@ -833,6 +836,9 @@
# CHECK-BE: mfocrf 16, 8 # encoding: [0x7e,0x10,0x80,0x26]
# CHECK-LE: mfocrf 16, 8 # encoding: [0x26,0x80,0x10,0x7e]
mfocrf 16, 8
+# CHECK-BE: mcrxrx 7 # encoding: [0x7f,0x80,0x04,0x80]
+# CHECK-LE: mcrxrx 7 # encoding: [0x80,0x04,0x80,0x7f]
+ mcrxrx 7
# Move to/from segment register
# CHECK-BE: mtsr 12, 10 # encoding: [0x7d,0x4c,0x01,0xa4]
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