[PATCH] D18566: [x86] use SSE/AVX ops for non-zero memsets (PR27100)

[Sanjay Patel via llvm-commits]

spatel updated this revision to Diff 52003.
spatel added a comment.

Patch updated:
Move the memset check down to the slow SSE case: this allows fast targets to take advantage of SSE/AVX instructions and prevents slow targets from stepping into a codegen sinkhole while trying to splat a byte into an XMM reg.

Note that, unlike the previous rev of the patch, all existing regression tests remain unchanged except for the tests that I added to model the request in PR27100.

We still have the questions of AVX1 codegen and unexpected machine scheduler behavior, but I think we can address those separately.


http://reviews.llvm.org/D18566

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/memset-nonzero.ll

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