[llvm] r264567 - [Power9] Implement new vsx instructions: insert, extract, test data class, min/max, reverse, permute, splat
Chuang-Yu Cheng via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 28 01:34:29 PDT 2016
Author: cycheng
Date: Mon Mar 28 03:34:28 2016
New Revision: 264567
URL: http://llvm.org/viewvc/llvm-project?rev=264567&view=rev
Log:
[Power9] Implement new vsx instructions: insert, extract, test data class, min/max, reverse, permute, splat
This change implements the following vsx instructions:
- Scalar Insert/Extract
xsiexpdp xsiexpqp xsxexpdp xsxsigdp xsxexpqp xsxsigqp
- Vector Insert/Extract
xviexpdp xviexpsp xvxexpdp xvxexpsp xvxsigdp xvxsigsp
xxextractuw xxinsertw
- Scalar/Vector Test Data Class
xststdcdp xststdcsp xststdcqp
xvtstdcdp xvtstdcsp
- Maximum/Minimum
xsmaxcdp xsmaxjdp
xsmincdp xsminjdp
- Vector Byte-Reverse/Permute/Splat
xxbrd xxbrh xxbrq xxbrw
xxperm xxpermr
xxspltib
30 instructions
Thanks Nemanja for invaluable discussion! Thanks Kit's great help!
Reviewers: hal, nemanja, kbarton, tjablin, amehsan
http://reviews.llvm.org/D16842
Modified:
llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
llvm/trunk/lib/Target/PowerPC/README_P9.txt
llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt
llvm/trunk/test/MC/PowerPC/vsx.s
Modified: llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp?rev=264567&r1=264566&r2=264567&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp Mon Mar 28 03:34:28 2016
@@ -458,9 +458,11 @@ public:
bool isU6ImmX2() const { return Kind == Immediate &&
isUInt<6>(getImm()) &&
(getImm() & 1) == 0; }
+ bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
bool isU7ImmX4() const { return Kind == Immediate &&
isUInt<7>(getImm()) &&
(getImm() & 3) == 0; }
+ bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
bool isU8ImmX8() const { return Kind == Immediate &&
isUInt<8>(getImm()) &&
(getImm() & 7) == 0; }
Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp?rev=264567&r1=264566&r2=264567&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp Mon Mar 28 03:34:28 2016
@@ -299,6 +299,20 @@ void PPCInstPrinter::printU6ImmOperand(c
O << (unsigned int)Value;
}
+void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
+ raw_ostream &O) {
+ unsigned int Value = MI->getOperand(OpNo).getImm();
+ assert(Value <= 127 && "Invalid u7imm argument!");
+ O << (unsigned int)Value;
+}
+
+void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
+ raw_ostream &O) {
+ unsigned int Value = MI->getOperand(OpNo).getImm();
+ assert(Value <= 255 && "Invalid u8imm argument!");
+ O << (unsigned int)Value;
+}
+
void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
unsigned short Value = MI->getOperand(OpNo).getImm();
Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h?rev=264567&r1=264566&r2=264567&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h (original)
+++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h Mon Mar 28 03:34:28 2016
@@ -53,6 +53,8 @@ public:
void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+ void printU7ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+ void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printU10ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printU12ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td?rev=264567&r1=264566&r2=264567&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td Mon Mar 28 03:34:28 2016
@@ -769,6 +769,37 @@ class X_RD5_XO5_RS5<bits<6> opcode, bits
let A = xo2;
}
+class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<3> BF;
+ bits<7> DCMX;
+ bits<5> VB;
+
+ let Pattern = pattern;
+
+ let Inst{6-8} = BF;
+ let Inst{9-15} = DCMX;
+ let Inst{16-20} = VB;
+ let Inst{21-30} = xo;
+ let Inst{31} = 0;
+}
+
+class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<6> XT;
+ bits<8> IMM8;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = XT{4-0};
+ let Inst{11-12} = 0;
+ let Inst{13-20} = IMM8;
+ let Inst{21-30} = xo;
+ let Inst{31} = XT{5};
+}
+
// XX*-Form (VSX)
class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
@@ -842,6 +873,41 @@ class XX2Form_2<bits<6> opcode, bits<9>
let Inst{31} = XT{5};
}
+class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<6> XT;
+ bits<6> XB;
+ bits<5> UIM5;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = XT{4-0};
+ let Inst{11-15} = UIM5;
+ let Inst{16-20} = XB{4-0};
+ let Inst{21-29} = xo;
+ let Inst{30} = XB{5};
+ let Inst{31} = XT{5};
+}
+
+// [PO T XO B XO BX /]
+class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<5> RT;
+ bits<6> XB;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = RT;
+ let Inst{11-15} = xo2;
+ let Inst{16-20} = XB{4-0};
+ let Inst{21-29} = xo;
+ let Inst{30} = XB{5};
+ let Inst{31} = 0;
+}
+
+// [PO T XO B XO BX TX]
class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> {
@@ -857,6 +923,44 @@ class XX2_RD6_XO5_RS6<bits<6> opcode, bi
let Inst{30} = XB{5};
let Inst{31} = XT{5};
}
+
+class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<3> BF;
+ bits<7> DCMX;
+ bits<6> XB;
+
+ let Pattern = pattern;
+
+ let Inst{6-8} = BF;
+ let Inst{9-15} = DCMX;
+ let Inst{16-20} = XB{4-0};
+ let Inst{21-29} = xo;
+ let Inst{30} = XB{5};
+ let Inst{31} = 0;
+}
+
+class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2,
+ dag OOL, dag IOL, string asmstr, InstrItinClass itin,
+ list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<6> XT;
+ bits<7> DCMX;
+ bits<6> XB;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = XT{4-0};
+ let Inst{11-15} = DCMX{4-0};
+ let Inst{16-20} = XB{4-0};
+ let Inst{21-24} = xo1;
+ let Inst{25} = DCMX{5};
+ let Inst{26-28} = xo2;
+ let Inst{29} = DCMX{6};
+ let Inst{30} = XB{5};
+ let Inst{31} = XT{5};
+}
class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=264567&r1=264566&r2=264567&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Mon Mar 28 03:34:28 2016
@@ -507,6 +507,24 @@ def u6imm : Operand<i32> {
let ParserMatchClass = PPCU6ImmAsmOperand;
let DecoderMethod = "decodeUImmOperand<6>";
}
+def PPCU7ImmAsmOperand : AsmOperandClass {
+ let Name = "U7Imm"; let PredicateMethod = "isU7Imm";
+ let RenderMethod = "addImmOperands";
+}
+def u7imm : Operand<i32> {
+ let PrintMethod = "printU7ImmOperand";
+ let ParserMatchClass = PPCU7ImmAsmOperand;
+ let DecoderMethod = "decodeUImmOperand<7>";
+}
+def PPCU8ImmAsmOperand : AsmOperandClass {
+ let Name = "U8Imm"; let PredicateMethod = "isU8Imm";
+ let RenderMethod = "addImmOperands";
+}
+def u8imm : Operand<i32> {
+ let PrintMethod = "printU8ImmOperand";
+ let ParserMatchClass = PPCU8ImmAsmOperand;
+ let DecoderMethod = "decodeUImmOperand<8>";
+}
def PPCU10ImmAsmOperand : AsmOperandClass {
let Name = "U10Imm"; let PredicateMethod = "isU10Imm";
let RenderMethod = "addImmOperands";
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td?rev=264567&r1=264566&r2=264567&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td Mon Mar 28 03:34:28 2016
@@ -1806,6 +1806,12 @@ let Predicates = [HasP9Vector] in {
: X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vbtype:$vB),
!strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>;
+ // [PO T XO B XO BX /]
+ class XX2_RT5_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,
+ list<dag> pattern>
+ : XX2_RD5_XO5_RS6<opcode, xo2, xo, (outs g8rc:$rT), (ins vsfrc:$XB),
+ !strconcat(opc, " $rT, $XB"), IIC_VecFP, pattern>;
+
// [PO T XO B XO BX TX]
class XX2_XT6_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,
RegisterOperand vtype, list<dag> pattern>
@@ -1968,6 +1974,99 @@ let Predicates = [HasP9Vector] in {
def XSRQPXP : Z23_VT5_R1_VB5_RMC2_EX1<63, 37, 0, "xsrqpxp", []>;
//===--------------------------------------------------------------------===//
+ // Insert/Extract Instructions
+
+ // Insert Exponent DP/QP
+ // XT NOTE: XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU
+ def XSIEXPDP : XX1Form <60, 918, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB),
+ "xsiexpdp $XT, $rA, $rB", IIC_VecFP, []>;
+ // vB NOTE: only vB.dword[0] is used, that's why we don't use
+ // X_VT5_VA5_VB5 form
+ def XSIEXPQP : XForm_18<63, 868, (outs vrrc:$vT), (ins vrrc:$vA, vsfrc:$vB),
+ "xsiexpqp $vT, $vA, $vB", IIC_VecFP, []>;
+
+ // Extract Exponent/Significand DP/QP
+ def XSXEXPDP : XX2_RT5_XO5_XB6<60, 0, 347, "xsxexpdp", []>;
+ def XSXSIGDP : XX2_RT5_XO5_XB6<60, 1, 347, "xsxsigdp", []>;
+ def XSXEXPQP : X_VT5_XO5_VB5 <63, 2, 804, "xsxexpqp", []>;
+ def XSXSIGQP : X_VT5_XO5_VB5 <63, 18, 804, "xsxsigqp", []>;
+
+ // Vector Insert Word
+ // XB NOTE: Only XB.dword[1] is used, but we use vsrc on XB.
+ def XXINSERTW : XX2_RD6_UIM5_RS6<60, 181,
+ (outs vsrc:$XT), (ins u4imm:$UIMM, vsrc:$XB),
+ "xxinsertw $XT, $XB, $UIMM", IIC_VecFP, []>;
+
+ // Vector Extract Unsigned Word
+ def XXEXTRACTUW : XX2_RD6_UIM5_RS6<60, 165,
+ (outs vsrc:$XT), (ins u4imm:$UIMM, vsrc:$XB),
+ "xxextractuw $XT, $XB, $UIMM", IIC_VecFP, []>;
+
+ // Vector Insert Exponent DP/SP
+ def XVIEXPDP : XX3_XT5_XA5_XB5<60, 248, "xviexpdp", vsrc, vsrc, vsrc,
+ IIC_VecFP, []>;
+ def XVIEXPSP : XX3_XT5_XA5_XB5<60, 216, "xviexpsp", vsrc, vsrc, vsrc,
+ IIC_VecFP, []>;
+
+ // Vector Extract Exponent/Significand DP/SP
+ def XVXEXPDP : XX2_XT6_XO5_XB6<60, 0, 475, "xvxexpdp", vsrc, []>;
+ def XVXEXPSP : XX2_XT6_XO5_XB6<60, 8, 475, "xvxexpsp", vsrc, []>;
+ def XVXSIGDP : XX2_XT6_XO5_XB6<60, 1, 475, "xvxsigdp", vsrc, []>;
+ def XVXSIGSP : XX2_XT6_XO5_XB6<60, 9, 475, "xvxsigsp", vsrc, []>;
+
+ //===--------------------------------------------------------------------===//
+
+ // Test Data Class SP/DP/QP
+ def XSTSTDCSP : XX2_BF3_DCMX7_RS6<60, 298,
+ (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB),
+ "xststdcsp $BF, $XB, $DCMX", IIC_VecFP, []>;
+ def XSTSTDCDP : XX2_BF3_DCMX7_RS6<60, 362,
+ (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB),
+ "xststdcdp $BF, $XB, $DCMX", IIC_VecFP, []>;
+ def XSTSTDCQP : X_BF3_DCMX7_RS5 <63, 708,
+ (outs crrc:$BF), (ins u7imm:$DCMX, vrrc:$vB),
+ "xststdcqp $BF, $vB, $DCMX", IIC_VecFP, []>;
+
+ // Vector Test Data Class SP/DP
+ def XVTSTDCSP : XX2_RD6_DCMX7_RS6<60, 13, 5,
+ (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB),
+ "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP, []>;
+ def XVTSTDCDP : XX2_RD6_DCMX7_RS6<60, 15, 5,
+ (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB),
+ "xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP, []>;
+
+ //===--------------------------------------------------------------------===//
+
+ // Maximum/Minimum Type-C/Type-J DP
+ // XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU, so we use vsrc for XT
+ def XSMAXCDP : XX3_XT5_XA5_XB5<60, 128, "xsmaxcdp", vsrc, vsfrc, vsfrc,
+ IIC_VecFP, []>;
+ def XSMAXJDP : XX3_XT5_XA5_XB5<60, 144, "xsmaxjdp", vsrc, vsfrc, vsfrc,
+ IIC_VecFP, []>;
+ def XSMINCDP : XX3_XT5_XA5_XB5<60, 136, "xsmincdp", vsrc, vsfrc, vsfrc,
+ IIC_VecFP, []>;
+ def XSMINJDP : XX3_XT5_XA5_XB5<60, 152, "xsminjdp", vsrc, vsfrc, vsfrc,
+ IIC_VecFP, []>;
+
+ //===--------------------------------------------------------------------===//
+
+ // Vector Byte-Reverse H/W/D/Q Word
+ def XXBRH : XX2_XT6_XO5_XB6<60, 7, 475, "xxbrh", vsrc, []>;
+ def XXBRW : XX2_XT6_XO5_XB6<60, 15, 475, "xxbrw", vsrc, []>;
+ def XXBRD : XX2_XT6_XO5_XB6<60, 23, 475, "xxbrd", vsrc, []>;
+ def XXBRQ : XX2_XT6_XO5_XB6<60, 31, 475, "xxbrq", vsrc, []>;
+
+ // Vector Permute
+ def XXPERM : XX3_XT5_XA5_XB5<60, 26, "xxperm" , vsrc, vsrc, vsrc,
+ IIC_VecPerm, []>;
+ def XXPERMR : XX3_XT5_XA5_XB5<60, 58, "xxpermr", vsrc, vsrc, vsrc,
+ IIC_VecPerm, []>;
+
+ // Vector Splat Immediate Byte
+ def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm:$IMM8),
+ "xxspltib $XT, $IMM8", IIC_VecPerm, []>;
+
+ //===--------------------------------------------------------------------===//
// Vector/Scalar Load/Store Instructions
let mayLoad = 1 in {
Modified: llvm/trunk/lib/Target/PowerPC/README_P9.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/README_P9.txt?rev=264567&r1=264566&r2=264567&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/README_P9.txt (original)
+++ llvm/trunk/lib/Target/PowerPC/README_P9.txt Mon Mar 28 03:34:28 2016
@@ -343,6 +343,112 @@ VSX:
. Provide builtin?
(set f128:$vT, (int_ppc_vsx_xsrqpxp f128:$vB))
+- Insert Exponent DP/QP: xsiexpdp xsiexpqp
+ . Use intrinsic?
+ . xsiexpdp:
+ // Note: rA and rB are the unsigned integer value.
+ (set f128:$XT, (int_ppc_vsx_xsiexpdp i64:$rA, i64:$rB))
+
+ . xsiexpqp:
+ (set f128:$vT, (int_ppc_vsx_xsiexpqp f128:$vA, f64:$vB))
+
+- Extract Exponent/Significand DP/QP: xsxexpdp xsxsigdp xsxexpqp xsxsigqp
+ . Use intrinsic?
+ . (set i64:$rT, (int_ppc_vsx_xsxexpdp f64$XB)) // xsxexpdp
+ (set i64:$rT, (int_ppc_vsx_xsxsigdp f64$XB)) // xsxsigdp
+ (set f128:$vT, (int_ppc_vsx_xsxexpqp f128$vB)) // xsxexpqp
+ (set f128:$vT, (int_ppc_vsx_xsxsigqp f128$vB)) // xsxsigqp
+
+- Vector Insert Word: xxinsertw
+ . Note: llvm has insertelem in "Vector Operations"
+ ; yields <n x <ty>>
+ <result> = insertelement <n x <ty>> <val>, <ty> <elt>, <ty2> <idx>
+
+ But how to map to it??
+ [(set v1f128:$XT, (insertelement v1f128:$XTi, f128:$XB, i4:$UIMM))]>,
+ RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+
+ . Or use intrinsic?
+ (set v1f128:$XT, (int_ppc_vsx_xxinsertw v1f128:$XTi, f128:$XB, i4:$UIMM))
+
+- Vector Extract Unsigned Word: xxextractuw
+ . Note: llvm has extractelement in "Vector Operations"
+ ; yields <ty>
+ <result> = extractelement <n x <ty>> <val>, <ty2> <idx>
+
+ How to map to it??
+ [(set f128:$XT, (extractelement v1f128:$XB, i4:$UIMM))]
+
+ . Or use intrinsic?
+ (set f128:$XT, (int_ppc_vsx_xxextractuw v1f128:$XB, i4:$UIMM))
+
+- Vector Insert Exponent DP/SP: xviexpdp xviexpsp
+ . Use intrinsic
+ (set v2f64:$XT, (int_ppc_vsx_xviexpdp v2f64:$XA, v2f64:$XB))
+ (set v4f32:$XT, (int_ppc_vsx_xviexpsp v4f32:$XA, v4f32:$XB))
+
+- Vector Extract Exponent/Significand DP/SP: xvxexpdp xvxexpsp xvxsigdp xvxsigsp
+ . Use intrinsic
+ (set v2f64:$XT, (int_ppc_vsx_xvxexpdp v2f64:$XB))
+ (set v4f32:$XT, (int_ppc_vsx_xvxexpsp v4f32:$XB))
+ (set v2f64:$XT, (int_ppc_vsx_xvxsigdp v2f64:$XB))
+ (set v4f32:$XT, (int_ppc_vsx_xvxsigsp v4f32:$XB))
+
+- Test Data Class SP/DP/QP: xststdcsp xststdcdp xststdcqp
+ . No SDAG, intrinsic, builtin are required?
+ Because it seems that we have no way to map BF field?
+
+ Instruction Form: [PO T XO B XO BX TX]
+ Asm: xststd* BF,XB,DCMX
+
+ BF is an index to CR register field.
+
+- Vector Test Data Class SP/DP: xvtstdcsp xvtstdcdp
+ . Use intrinsic
+ (set v4f32:$XT, (int_ppc_vsx_xvtstdcsp v4f32:$XB, i7:$DCMX))
+ (set v2f64:$XT, (int_ppc_vsx_xvtstdcdp v2f64:$XB, i7:$DCMX))
+
+- Maximum/Minimum Type-C/Type-J DP: xsmaxcdp xsmaxjdp xsmincdp xsminjdp
+ . PowerISA_V3.0:
+ "xsmaxcdp can be used to implement the C/C++/Java conditional operation
+ (x>y)?x:y for single-precision and double-precision arguments."
+
+ Note! c type and j type have different behavior when:
+ 1. Either input is NaN
+ 2. Both input are +-Infinity, +-Zero
+
+ . dtype map to llvm fmaxnum/fminnum
+ jtype use intrinsic
+
+ . xsmaxcdp xsmincdp
+ (set f64:$XT, (fmaxnum f64:$XA, f64:$XB))
+ (set f64:$XT, (fminnum f64:$XA, f64:$XB))
+
+ . xsmaxjdp xsminjdp
+ (set f64:$XT, (int_ppc_vsx_xsmaxjdp f64:$XA, f64:$XB))
+ (set f64:$XT, (int_ppc_vsx_xsminjdp f64:$XA, f64:$XB))
+
+- Vector Byte-Reverse H/W/D/Q Word: xxbrh xxbrw xxbrd xxbrq
+ . Use intrinsic
+ (set v8i16:$XT, (int_ppc_vsx_xxbrh v8i16:$XB))
+ (set v4i32:$XT, (int_ppc_vsx_xxbrw v4i32:$XB))
+ (set v2i64:$XT, (int_ppc_vsx_xxbrd v2i64:$XB))
+ (set v1i128:$XT, (int_ppc_vsx_xxbrq v1i128:$XB))
+
+- Vector Permute: xxperm xxpermr
+ . I have checked "PPCxxswapd" in PPCInstrVSX.td, but they are different
+ . Use intrinsic
+ (set v16i8:$XT, (int_ppc_vsx_xxperm v16i8:$XA, v16i8:$XB))
+ (set v16i8:$XT, (int_ppc_vsx_xxpermr v16i8:$XA, v16i8:$XB))
+
+- Vector Splat Immediate Byte: xxspltib
+ . Similar to XXSPLTW:
+ def XXSPLTW : XX2Form_2<60, 164,
+ (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM),
+ "xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>;
+
+ . No SDAG, intrinsic, builtin are required?
+
- Load/Store Vector: lxv stxv
. Has likely SDAG match:
(set v?:$XT, (load ix16addr:$src))
Modified: llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt?rev=264567&r1=264566&r2=264567&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt (original)
+++ llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt Mon Mar 28 03:34:28 2016
@@ -692,6 +692,99 @@
# CHECK: xsrqpxp 1, 7, 27, 2
0xfc 0xe1 0xdc 0x4a
+# CHECK: xsiexpdp 63, 3, 4
+0xf3 0xe3 0x27 0x2d
+
+# CHECK: xsiexpqp 7, 31, 27
+0xfc 0xff 0xde 0xc8
+
+# CHECK: xviexpdp 7, 63, 27
+0xf0 0xff 0xdf 0xc4
+
+# CHECK: xviexpsp 7, 63, 27
+0xf0 0xff 0xde 0xc4
+
+# CHECK: xxextractuw 7, 63, 15
+0xf0 0xef 0xfa 0x96
+
+# CHECK: xxinsertw 7, 63, 15
+0xf0 0xef 0xfa 0xd6
+
+# CHECK: xsxexpdp 7, 63
+0xf0 0xe0 0xfd 0x6e
+
+# CHECK: xsxsigdp 7, 63
+0xf0 0xe1 0xfd 0x6e
+
+# CHECK: xsxexpqp 7, 31
+0xfc 0xe2 0xfe 0x48
+
+# CHECK: xsxsigqp 7, 31
+0xfc 0xf2 0xfe 0x48
+
+# CHECK: xvxexpdp 7, 63
+0xf0 0xe0 0xff 0x6e
+
+# CHECK: xvxexpsp 7, 63
+0xf0 0xe8 0xff 0x6e
+
+# CHECK: xvxsigdp 7, 63
+0xf0 0xe1 0xff 0x6e
+
+# CHECK: xvxsigsp 7, 63
+0xf0 0xe9 0xff 0x6e
+
+# CHECK: xststdcsp 7, 63, 127
+0xf3 0xff 0xfc 0xaa
+
+# CHECK: xststdcdp 7, 63, 127
+0xf3 0xff 0xfd 0xaa
+
+# CHECK: xststdcqp 7, 31, 127
+0xff 0xff 0xfd 0x88
+
+# CHECK: xststdcsp 7, 63, 127
+0xf3 0xff 0xfc 0xaa
+
+# CHECK: xststdcdp 7, 63, 127
+0xf3 0xff 0xfd 0xaa
+
+# CHECK: xststdcqp 7, 31, 127
+0xff 0xff 0xfd 0x88
+
+# CHECK: xsmaxcdp 7, 63, 27
+0xf0 0xff 0xdc 0x04
+
+# CHECK: xsmaxjdp 7, 63, 27
+0xf0 0xff 0xdc 0x84
+
+# CHECK: xsmincdp 7, 63, 27
+0xf0 0xff 0xdc 0x44
+
+# CHECK: xsminjdp 7, 63, 27
+0xf0 0xff 0xdc 0xc4
+
+# CHECK: xxbrh 7, 63
+0xf0 0xe7 0xff 0x6e
+
+# CHECK: xxbrw 7, 63
+0xf0 0xef 0xff 0x6e
+
+# CHECK: xxbrd 7, 63
+0xf0 0xf7 0xff 0x6e
+
+# CHECK: xxbrq 7, 63
+0xf0 0xff 0xff 0x6e
+
+# CHECK: xxperm 7, 63, 27
+0xf0 0xff 0xd8 0xd4
+
+# CHECK: xxpermr 7, 63, 27
+0xf0 0xff 0xd9 0xd4
+
+# CHECK: xxspltib 63, 255
+0xf3 0xe7 0xfa 0xd1
+
# CHECK: lxv 61, 32752(31)
0xf7 0xbf 0x7f 0xf9
Modified: llvm/trunk/test/MC/PowerPC/vsx.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/vsx.s?rev=264567&r1=264566&r2=264567&view=diff
==============================================================================
--- llvm/trunk/test/MC/PowerPC/vsx.s (original)
+++ llvm/trunk/test/MC/PowerPC/vsx.s Mon Mar 28 03:34:28 2016
@@ -732,6 +732,123 @@
# CHECK-LE: xsrqpxp 1, 7, 27, 2 # encoding: [0x4a,0xdc,0xe1,0xfc]
xsrqpxp 1, 7, 27, 2
+# Insert Exponent DP/QP
+# CHECK-BE: xsiexpdp 63, 3, 4 # encoding: [0xf3,0xe3,0x27,0x2d]
+# CHECK-LE: xsiexpdp 63, 3, 4 # encoding: [0x2d,0x27,0xe3,0xf3]
+ xsiexpdp 63, 3, 4
+# CHECK-BE: xsiexpqp 7, 31, 27 # encoding: [0xfc,0xff,0xde,0xc8]
+# CHECK-LE: xsiexpqp 7, 31, 27 # encoding: [0xc8,0xde,0xff,0xfc]
+ xsiexpqp 7, 31, 27
+
+# Vector Insert Exponent DP
+# CHECK-BE: xviexpdp 7, 63, 27 # encoding: [0xf0,0xff,0xdf,0xc4]
+# CHECK-LE: xviexpdp 7, 63, 27 # encoding: [0xc4,0xdf,0xff,0xf0]
+ xviexpdp 7, 63, 27
+# CHECK-BE: xviexpsp 7, 63, 27 # encoding: [0xf0,0xff,0xde,0xc4]
+# CHECK-LE: xviexpsp 7, 63, 27 # encoding: [0xc4,0xde,0xff,0xf0]
+ xviexpsp 7, 63, 27
+
+# Vector Extract Unsigned Word
+# CHECK-BE: xxextractuw 7, 63, 15 # encoding: [0xf0,0xef,0xfa,0x96]
+# CHECK-LE: xxextractuw 7, 63, 15 # encoding: [0x96,0xfa,0xef,0xf0]
+ xxextractuw 7, 63, 15
+
+# Vector Insert Word
+# CHECK-BE: xxinsertw 7, 63, 15 # encoding: [0xf0,0xef,0xfa,0xd6]
+# CHECK-LE: xxinsertw 7, 63, 15 # encoding: [0xd6,0xfa,0xef,0xf0]
+ xxinsertw 7, 63, 15
+
+# Extract Exponent/Significand DP/QP
+# CHECK-BE: xsxexpdp 7, 63 # encoding: [0xf0,0xe0,0xfd,0x6e]
+# CHECK-LE: xsxexpdp 7, 63 # encoding: [0x6e,0xfd,0xe0,0xf0]
+ xsxexpdp 7, 63
+# CHECK-BE: xsxsigdp 7, 63 # encoding: [0xf0,0xe1,0xfd,0x6e]
+# CHECK-LE: xsxsigdp 7, 63 # encoding: [0x6e,0xfd,0xe1,0xf0]
+ xsxsigdp 7, 63
+# CHECK-BE: xsxexpqp 7, 31 # encoding: [0xfc,0xe2,0xfe,0x48]
+# CHECK-LE: xsxexpqp 7, 31 # encoding: [0x48,0xfe,0xe2,0xfc]
+ xsxexpqp 7, 31
+# CHECK-BE: xsxsigqp 7, 31 # encoding: [0xfc,0xf2,0xfe,0x48]
+# CHECK-LE: xsxsigqp 7, 31 # encoding: [0x48,0xfe,0xf2,0xfc]
+ xsxsigqp 7, 31
+
+# Vector Extract Exponent/Significand DP
+# CHECK-BE: xvxexpdp 7, 63 # encoding: [0xf0,0xe0,0xff,0x6e]
+# CHECK-LE: xvxexpdp 7, 63 # encoding: [0x6e,0xff,0xe0,0xf0]
+ xvxexpdp 7, 63
+# CHECK-BE: xvxexpsp 7, 63 # encoding: [0xf0,0xe8,0xff,0x6e]
+# CHECK-LE: xvxexpsp 7, 63 # encoding: [0x6e,0xff,0xe8,0xf0]
+ xvxexpsp 7, 63
+# CHECK-BE: xvxsigdp 7, 63 # encoding: [0xf0,0xe1,0xff,0x6e]
+# CHECK-LE: xvxsigdp 7, 63 # encoding: [0x6e,0xff,0xe1,0xf0]
+ xvxsigdp 7, 63
+# CHECK-BE: xvxsigsp 7, 63 # encoding: [0xf0,0xe9,0xff,0x6e]
+# CHECK-LE: xvxsigsp 7, 63 # encoding: [0x6e,0xff,0xe9,0xf0]
+ xvxsigsp 7, 63
+
+# Test Data Class SP/DP/QP
+# CHECK-BE: xststdcsp 7, 63, 127 # encoding: [0xf3,0xff,0xfc,0xaa]
+# CHECK-LE: xststdcsp 7, 63, 127 # encoding: [0xaa,0xfc,0xff,0xf3]
+ xststdcsp 7, 63, 127
+# CHECK-BE: xststdcdp 7, 63, 127 # encoding: [0xf3,0xff,0xfd,0xaa]
+# CHECK-LE: xststdcdp 7, 63, 127 # encoding: [0xaa,0xfd,0xff,0xf3]
+ xststdcdp 7, 63, 127
+# CHECK-BE: xststdcqp 7, 31, 127 # encoding: [0xff,0xff,0xfd,0x88]
+# CHECK-LE: xststdcqp 7, 31, 127 # encoding: [0x88,0xfd,0xff,0xff]
+ xststdcqp 7, 31, 127
+
+# Vector Test Data Class SP/DP
+# CHECK-BE: xststdcsp 7, 63, 127 # encoding: [0xf3,0xff,0xfc,0xaa]
+# CHECK-LE: xststdcsp 7, 63, 127 # encoding: [0xaa,0xfc,0xff,0xf3]
+ xststdcsp 7, 63, 127
+# CHECK-BE: xststdcdp 7, 63, 127 # encoding: [0xf3,0xff,0xfd,0xaa]
+# CHECK-LE: xststdcdp 7, 63, 127 # encoding: [0xaa,0xfd,0xff,0xf3]
+ xststdcdp 7, 63, 127
+# CHECK-BE: xststdcqp 7, 31, 127 # encoding: [0xff,0xff,0xfd,0x88]
+# CHECK-LE: xststdcqp 7, 31, 127 # encoding: [0x88,0xfd,0xff,0xff]
+ xststdcqp 7, 31, 127
+
+# Maximum/Minimum Type-C/Type-J DP
+# CHECK-BE: xsmaxcdp 7, 63, 27 # encoding: [0xf0,0xff,0xdc,0x04]
+# CHECK-LE: xsmaxcdp 7, 63, 27 # encoding: [0x04,0xdc,0xff,0xf0]
+ xsmaxcdp 7, 63, 27
+# CHECK-BE: xsmaxjdp 7, 63, 27 # encoding: [0xf0,0xff,0xdc,0x84]
+# CHECK-LE: xsmaxjdp 7, 63, 27 # encoding: [0x84,0xdc,0xff,0xf0]
+ xsmaxjdp 7, 63, 27
+# CHECK-BE: xsmincdp 7, 63, 27 # encoding: [0xf0,0xff,0xdc,0x44]
+# CHECK-LE: xsmincdp 7, 63, 27 # encoding: [0x44,0xdc,0xff,0xf0]
+ xsmincdp 7, 63, 27
+# CHECK-BE: xsminjdp 7, 63, 27 # encoding: [0xf0,0xff,0xdc,0xc4]
+# CHECK-LE: xsminjdp 7, 63, 27 # encoding: [0xc4,0xdc,0xff,0xf0]
+ xsminjdp 7, 63, 27
+
+# Vector Byte-Reverse H/W/D/Q Word
+# CHECK-BE: xxbrh 7, 63 # encoding: [0xf0,0xe7,0xff,0x6e]
+# CHECK-LE: xxbrh 7, 63 # encoding: [0x6e,0xff,0xe7,0xf0]
+ xxbrh 7, 63
+# CHECK-BE: xxbrw 7, 63 # encoding: [0xf0,0xef,0xff,0x6e]
+# CHECK-LE: xxbrw 7, 63 # encoding: [0x6e,0xff,0xef,0xf0]
+ xxbrw 7, 63
+# CHECK-BE: xxbrd 7, 63 # encoding: [0xf0,0xf7,0xff,0x6e]
+# CHECK-LE: xxbrd 7, 63 # encoding: [0x6e,0xff,0xf7,0xf0]
+ xxbrd 7, 63
+# CHECK-BE: xxbrq 7, 63 # encoding: [0xf0,0xff,0xff,0x6e]
+# CHECK-LE: xxbrq 7, 63 # encoding: [0x6e,0xff,0xff,0xf0]
+ xxbrq 7, 63
+
+# Vector Permute
+# CHECK-BE: xxperm 7, 63, 27 # encoding: [0xf0,0xff,0xd8,0xd4]
+# CHECK-LE: xxperm 7, 63, 27 # encoding: [0xd4,0xd8,0xff,0xf0]
+ xxperm 7, 63, 27
+# CHECK-BE: xxpermr 7, 63, 27 # encoding: [0xf0,0xff,0xd9,0xd4]
+# CHECK-LE: xxpermr 7, 63, 27 # encoding: [0xd4,0xd9,0xff,0xf0]
+ xxpermr 7, 63, 27
+
+# Vector Splat Immediate Byte
+# CHECK-BE: xxspltib 63, 255 # encoding: [0xf3,0xe7,0xfa,0xd1]
+# CHECK-LE: xxspltib 63, 255 # encoding: [0xd1,0xfa,0xe7,0xf3]
+ xxspltib 63, 255
+
# Load/Store Vector, test maximum and minimum displacement value
# CHECK-BE: lxv 61, 32752(31) # encoding: [0xf7,0xbf,0x7f,0xf9]
# CHECK-LE: lxv 61, 32752(31) # encoding: [0xf9,0x7f,0xbf,0xf7]
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