[PATCH] D18508: Replace at most one dead register with zero register on aarch64
Yichao Yu via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 27 20:59:58 PDT 2016
yuyichao created this revision.
yuyichao added a reviewer: t.p.northover.
yuyichao added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson.
As mentioned in my comment of the bug report, this seems to be fix the problem but it does make a few assumptions. This is currently assuming that no live dest can be zero register before this pass and there shouldn't be more than one dead register in other instructions.
I searched through the aarch64 instruction set manual and it seems that the load pair instructions are the only ones that can cause this trouble so maybe it is best to just check for those.
@@ -123,6 +123,8 @@
+ // Only replace one dead register
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